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Author	SHA1	Message	Date
Florent Kermarrec	5737aaa67c	ci: migrate from Travis-CI to Github Actions.	2020-11-24 13:36:06 +01:00
Florent Kermarrec	b1fd3e8092	bench/targets: increase buffer_depth to 256.	2020-11-24 10:19:52 +01:00
Florent Kermarrec	ca4284f977	bench: add colorlight_5a_75b test target.	2020-11-24 10:19:23 +01:00
Florent Kermarrec	c6cfed6294	frontend/etherbone: expose buffer_depth to user.	2020-11-23 17:44:47 +01:00
Florent Kermarrec	47100c5c4e	bench/test_etherbone: add initial speed_test.	2020-11-23 17:36:54 +01:00
Florent Kermarrec	3645d2f85f	bench: add initial test_etherbone.	2020-11-23 17:11:52 +01:00
Florent Kermarrec	c7d7561a38	bench/targets: add identifier and SRAM.	2020-11-23 17:11:36 +01:00
Florent Kermarrec	291b257eb4	phy/crg: make rst_n optional on all PHYs and minor cleanup.	2020-11-23 16:24:44 +01:00
enjoy-digital	75495dd6ec	Merge pull request #54 from rprinz08/master ... Fix syntax and load error in Wireshark etherbone dissector	2020-11-23 13:44:57 +01:00
Florent Kermarrec	41b0f0c774	add initial bench directory with minimal arty/genesys2 test targets.	2020-11-23 13:40:54 +01:00
Florent Kermarrec	53057121e7	examples: remove old examples and update README (new benches/examples will be added).	2020-11-23 12:54:09 +01:00
Florent Kermarrec	5247a2008a	phy/ecp5rgmii: remove p_DEL_MODE (not required since we specify DEL_VALUE).	2020-11-23 12:16:07 +01:00
rprinz08	d3bbd506ba	Fix syntax and load error in Wireshark etherbone dissector	2020-11-07 10:55:21 +01:00
Florent Kermarrec	06242564f7	frontend/etherbone: simplify LiteEthEtherboneRecordReceiver.	2020-11-06 19:49:07 +01:00
Florent Kermarrec	d96fdfc5e5	frontend/etherbone: simplify LiteEthEtherboneRecordSender using combinatorial logic and fix #52.	2020-11-06 19:43:57 +01:00
enjoy-digital	0c287d07f8	Merge pull request #51 from gregdavill/ecp5rgmii_delay_fix ... phy/ecp5rgmii: Fix io delay blocks	2020-10-12 09:17:02 +02:00
enjoy-digital	7fa06adf78	Merge pull request #48 from kbeckmann/fix_test ... test_etherbone: Fix import of etherbone module	2020-10-12 09:05:05 +02:00
enjoy-digital	317154f68f	Merge pull request #49 from gregdavill/ecp5_timing_fix ... mac/core: Improve timing closure of core	2020-10-12 09:04:34 +02:00
Greg Davill	6ee11edb87	phy/ecp5rgmii: Fix io delay blocks ... For correct io delays in nextpnr the DEL_VALUE parameter needs to be an integer, instead of the "DELAY{}" string. The use of a "DELAY{}" string appears in the Lattice primitive manual, but appears to be incorrect. At least based of the current nextpnr. Because we are not making use of dynamic io delays here we can also use the simpler DELAYG block instead of DELAYF. Fixes #50	2020-10-11 15:16:58 +10:30
Greg Davill	9aee36939f	mac/core: Improve timing closure of core ... On ECP5 targets the core struggles to meet timing closure. This change adds buffers to the CRC module on tx/rx paths. This results in 20-30MHz gain to max clock rate. This fixes #47	2020-10-11 14:46:16 +10:30
Konrad Beckmann	054eebc25f	test_etherbone: Fix import of etherbone module	2020-09-30 21:04:11 +02:00
Florent Kermarrec	54acf9fd76	phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). ... 3768f5acc1	2020-08-24 22:14:35 +02:00
Florent Kermarrec	64b85e621e	add SPDX License identifier to header and specify file is part or LiteEth. ... Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.	2020-08-23 16:07:12 +02:00
Florent Kermarrec	f275af8297	liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios.	2020-08-22 21:22:02 +02:00
enjoy-digital	0705b35399	Merge pull request #46 from Xiretza/gen-py-wishbone ... Update gen.py to work with latest LiteX in wishbone mode	2020-08-22 21:16:22 +02:00
Xiretza	6a9a5132f6	Update gen.py to work with latest LiteX in wishbone mode ... Previously, it would fail with: $ liteeth/gen.py examples/wishbone_mii.yml [snip] Traceback (most recent call last): File "liteeth/gen.py", line 346, in <module> main() File "liteeth/gen.py", line 331, in main soc = MACCore(platform, core_config) File "liteeth/gen.py", line 244, in __init__ self.add_wb_master(bridge.wishbone) File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master self.bus.add_master(master=wbm) File "[...]/litex/soc/integration/soc.py", line 347, in add_master master = self.add_adapter(name, master, "m2s") File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter bridge_cls = { KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)	2020-08-22 11:00:42 +02:00
Florent Kermarrec	792013a175	mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43).	2020-07-13 11:27:25 +02:00
Florent Kermarrec	1d76d02ea6	frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).	2020-07-13 10:08:50 +02:00
enjoy-digital	dbe15f17fc	Merge pull request #42 from shuffle2/padding ... mac padding: fix counter reset value	2020-06-26 15:43:07 +02:00
Shawn Hoffman	d66d302567	mac padding: fix counter reset value	2020-06-25 03:26:37 -07:00
Florent Kermarrec	b1bcfb2073	mac/LiteEthMACCoreCrossbar: remove unnecessary fifos.	2020-06-22 14:54:26 +02:00
Florent Kermarrec	8e1185711b	common: remove Port.connect and use 2 separate Record.connect.	2020-06-22 14:36:44 +02:00
Florent Kermarrec	17caf17c9e	mac/LiteEthMACCoreCrossbar: remove cpu_dw.	2020-06-19 22:06:53 +02:00
Florent Kermarrec	23b420a2dd	mac/LiteEthMAC: simplify hybrid mode and avoid some duplication.	2020-06-19 22:01:22 +02:00
Florent Kermarrec	51cd54602b	core/mac: add missing separators, fix typos.	2020-06-19 19:59:53 +02:00
Florent Kermarrec	59d3336bec	mac: add separators, improve indent, minor simplifications.	2020-06-19 19:42:25 +02:00
Florent Kermarrec	d06c7b49a2	frontend: add separators, improve indent, minor simplifications.	2020-06-19 19:21:24 +02:00
Florent Kermarrec	2d58f489ea	core: improve indent.	2020-06-19 19:12:12 +02:00
Florent Kermarrec	c26281882a	core: add separators.	2020-06-19 19:02:28 +02:00
Florent Kermarrec	bb29706e71	core: remove mac retro-compatibility (>6 months old).	2020-06-19 18:57:11 +02:00
Florent Kermarrec	0feed1720d	phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). ... This makes clocking more flexible and allows routing on more boards (ex: Pano Logic G2). Since TX clocking does not need clock phase relationship with the input clock using a combinatorial path is fine.	2020-05-29 10:39:18 +02:00
Florent Kermarrec	53c9eb91a5	core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue.	2020-05-19 10:13:15 +02:00
enjoy-digital	58e1681f5d	Merge pull request #41 from shuffle2/mcast ... iptx: support multicast mac and bypass arp table	2020-05-19 09:51:11 +02:00
Florent Kermarrec	8afdec936d	phy/ecp5rgmii: review/simplify inband_status integration. ... For now keep it specific to ECP5, we'll integrate this soon on the others PHYs, but some other refactoring/merging is required before.	2020-05-19 09:41:09 +02:00
enjoy-digital	55af430640	Merge pull request #40 from shuffle2/master ... ecp5rgmii: enable reading inband PHY_status	2020-05-19 08:36:59 +02:00
Shawn Hoffman	6d00ec1cc4	iptx: support multicast mac and bypass arp table	2020-05-17 14:52:02 -07:00
Shawn Hoffman	26c4e41b96	ecp5rgmii: enable reading inband PHY_status	2020-05-11 03:01:50 -07:00
Florent Kermarrec	dc67e6d070	phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5.	2020-04-22 10:14:36 +02:00
Florent Kermarrec	705003e523	README: switch to markdown.	2020-04-11 19:19:03 +02:00
Florent Kermarrec	92c30489ae	examples: use CRG from litex.build.	2020-04-10 10:31:14 +02:00