a189b2c195
phy/s6rgmii: fix missing last signal
2016-03-29 16:53:37 +02:00
b394f2f45e
test/mac_wishbone_tb: fix simulation
2016-03-25 12:26:02 +01:00
b7f3b3ef42
test: finish etherbone_tb (simulator limitation removed)
2016-03-23 09:48:02 +01:00
87924c84e6
test: finish mac_wishbone_tb (simulator limitation removed)
2016-03-23 09:47:47 +01:00
7ea1b5a22d
test: use passive generators and some cleanup
2016-03-23 01:42:35 +01:00
e73f35c733
test: remove __init__.py and use setup.py develop
2016-03-22 10:34:28 +01:00
2f15f3748e
test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE)
2016-03-21 19:59:29 +01:00
657ba4cb16
global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 21:36:07 +01:00
9cd7dc3088
global: use SyncFIFO instead of Buffer
2016-03-16 19:45:43 +01:00
aff07c6809
global: use new StrideConverter
2016-03-16 17:01:13 +01:00
51f56e79dd
global: remove use of sop
2016-03-16 16:22:00 +01:00
1f46aaeb55
core/mac: remove frontend directory (too much directories) and some cleanup
2016-03-15 20:09:30 +01:00
c3e15e7f7b
core/mac: use fifo_depth of 64 for all phys
2016-03-15 19:41:53 +01:00
32243934fb
global: use stream.Endpoint instead of Sink/Source (deprecated)
2016-03-15 16:50:00 +01:00
9593e29756
global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses
2016-03-15 15:40:06 +01:00
b7efe0fd46
phy: remove pads_register parameter (does not save enough, priority to simplicity)
2016-03-15 15:33:36 +01:00
5583fe5543
phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer
2016-02-24 23:51:31 +01:00
1dae2b802c
example_design/targets/core: cleanup
2016-02-10 10:50:38 +01:00
36399d65da
example_designs/targets/core: add possibility to build udp cores (with hw udp/ip stack)
2016-02-10 10:29:23 +01:00
fef1be9c35
example_designs/targets: add Makefile to build cores
2016-02-10 10:27:11 +01:00
59bfdd3d7f
example_design/targets/core: add RMII/GMII/RGMII support
2016-02-07 23:16:26 +01:00
989ae268ec
example_designs: add simple core generation example (MII / Wishbone)
2016-02-07 10:29:28 +01:00
d38612db0c
remove use of Record.connect
2015-12-27 12:26:01 +01:00
4cb6a20291
setup.py: exclude test directory
2015-12-19 21:06:15 +01:00
b8b04ccc31
example_designs/make.py: do not use "-" in build_name
2015-12-12 16:49:48 +01:00
1f19518d63
phy/common: add LiteEthPHYHWReset and use it on phys
2015-12-09 16:57:02 +01:00
54d7c6620b
phy: add mdio on all phys
2015-12-09 16:42:35 +01:00
ad0b4a165f
phy: rmii refactor (tested)
2015-12-07 15:46:15 +01:00
17ce01b58e
core/mac/core: use fifo depth of 8 for RMII phy
2015-12-04 09:38:59 +01:00
6006186fe0
phy/rmii: use 50MHz (instead of 100Mhz) and use DDROutput to generate ref_clk
2015-12-03 23:47:08 +01:00
09e6b3a8d7
phy: add s7rgmii
2015-12-01 01:34:06 +01:00
6b39b0f674
phy: fix clock domains renaming (ClockDomainsRenamer refactoring issue)
2015-11-30 13:04:47 +01:00
133cb88ead
common: small cleanup
2015-11-27 19:51:26 +01:00
449d84bf11
remove Counter module
2015-11-24 21:02:07 +01:00
9a7039ef72
use mininal imports
2015-11-24 20:44:00 +01:00
09dad1b520
phy/rmii: adapt to new syntax and fixes
2015-11-19 15:42:51 +01:00
f1725d5fd1
ethetbone software is now integrated in LiteX
2015-11-17 12:04:04 +01:00
155be56f9c
test: use new RemoteClient/RemoveServer provided by LiteX
2015-11-17 00:21:08 +01:00
34b6994d3c
stream/SyncFIFO now exposes fifo level
2015-11-16 16:12:41 +01:00
94e5c254eb
fix some imports
2015-11-14 20:17:47 +01:00
fda5ea0522
update setup.py
2015-11-14 17:28:40 +01:00
c1d7f2d427
phy: rename sim to model and remove from autodetect
2015-11-14 03:43:27 +01:00
88e18dfa23
doc: remove skeleton and change logo (we'll add a better doc later)
2015-11-14 00:58:43 +01:00
e7caf8acfb
use stream_packet and stream_sim from litex
2015-11-14 00:42:33 +01:00
b370c8b2f5
use stream_packet and stream_sim from litex
2015-11-14 00:35:38 +01:00
3f9e4d7882
README: update
2015-11-13 23:51:23 +01:00
d84d610104
simulations working with litex and vpi
2015-11-13 15:11:57 +01:00
7b9dc92b0b
for now use our fork of migen
2015-11-13 14:48:53 +01:00
886108eee9
test: for now revert all simulation (we'll switch when missing feature of new simulator will be implemted)
2015-11-13 14:47:57 +01:00
57b70c640c
start adapting simulations to new migen (still some issues with Migen simulator)
...
Simulator issues:
- MultiReg not simulated correctly (I've used direct instantiation of MultiRegImpl to get simulation working)
- MemoryArray with granularity != 1 raise NotImplementedError
2015-11-13 13:46:05 +01:00
Florent Kermarrec