dc8ddf6895
examples: keep up to date with LiteX
2019-11-23 15:23:24 +01:00
91f0f4ce80
test/model: improve presentation/readability
2019-11-23 15:17:22 +01:00
36c9951235
test: regroup model tests in test_model and run it with Travis-CI
2019-11-23 14:55:55 +01:00
7f31186b8c
add Travis-CI
2019-11-23 00:16:01 +01:00
bd1ead88d1
test: update for ci, for now disable test_etherbone since does not seem to finish
2019-11-23 00:14:19 +01:00
5a789570be
mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful)
2019-11-23 00:12:46 +01:00
57be29e68a
global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links
...
To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle.
Pass dw to all modules to allow making use of it in the future. For now dw=8.
2019-11-21 11:01:55 +01:00
ba83253ffa
core/arp: fix typo
2019-11-21 11:01:53 +01:00
6b0a9251c0
global: keep up to date with LiteX (update stream_packet import to packet)
...
Retro-compatibily was ensure by LiteX but update it.
2019-11-21 11:01:50 +01:00
5bf218a00b
Merge pull request #23 from enjoy-digital/versa_ecp5_udp_loopback
...
Versa ecp5 udp loopback example
2019-11-20 09:44:15 +01:00
e980b603cc
example/udp_loopback: simplify/cleanup and make it more generic
2019-11-20 08:53:16 +01:00
50cc7d0671
examples: add practical UDP loopback example with Versa ECP5
2019-11-20 08:18:50 +01:00
d2eb870445
core: allow passing ip_address as str
2019-11-07 13:23:10 +01:00
4d9e74f10a
phy/usrgmii: cleanup (style, indent)
2019-09-28 22:16:07 +02:00
4bc79cefd8
examples/targets/core: update
2019-09-24 12:53:06 +02:00
cd0eaa9607
Merge pull request #19 from jersey99/master
...
Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940
2019-09-05 11:07:59 +02:00
59e04608a8
Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940
2019-09-04 15:11:20 -07:00
ad187d35f2
add CONTRIBUTORS file and add copyright header to all files
2019-06-24 11:43:10 +02:00
fd6d6c30ba
mac: update imports
2019-06-24 11:23:13 +02:00
a170acda0f
change MAC location (next to phy/core/frontend), keep import retro-compatibility
2019-06-24 11:20:46 +02:00
789dadd8bf
liteeth/software: remove libwip/libuip examples.
...
libuip integration can be found in https://github.com/timvideos/HDMI2USB-litex-firmware/tree/master/firmware
2019-06-17 21:17:52 +02:00
2424e62bf9
software: also include generated/mem.h
2019-05-20 09:00:25 +02:00
e88fc507c8
software: remote ethmac_mem.h dependency (no longer exists in LiteX)
2019-05-19 19:29:04 +02:00
b318300414
phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked
2019-04-11 21:51:09 +02:00
e6c35cdec8
phy/ku_1000basex: incease pll_reset
2019-04-10 15:38:21 +02:00
816f592469
phy: add initial ECP5RGMII PHY
2019-02-25 14:45:19 +01:00
b4c1cfe8c5
core/icmp: fix reply checksum when request checksum >= 0xf800
...
need to add +1
2019-02-24 23:30:46 +01:00
77fa4bfb1e
phy: add Kintex7 1000BaseX PHY
2019-01-22 19:40:32 +01:00
c2d8a467c9
phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd)
2019-01-21 11:27:33 +01:00
d7fdcbb1dc
phy: add Spartan6 RGMII PHY
2018-12-18 08:58:16 +01:00
52c23015b0
frontend/etherbone: reduce default buffer_depth to 4
2018-10-30 11:21:06 +01:00
602ddec664
common: use reverse_bytes from litex.gen
2018-10-30 11:13:09 +01:00
40b99ecc05
test: use new RemoteClient import
2018-09-23 10:28:50 +02:00
c370e9f71f
phy/model: remove creation/deletion of ethernet tap (now handled by the simulator)
2018-09-20 22:49:37 +02:00
3d868449e9
core/mac/sram: fix code refactoring
2018-09-17 09:10:59 +02:00
5106bcdc0c
core/mac/sram: simplify last_be code
2018-09-07 21:14:17 +02:00
ce72e34f56
core/mac: pass endianness and use if for last_be gen/check
2018-09-07 10:35:27 +02:00
94af3d63d9
README: update and rename example_designs to examples
2018-08-31 08:26:37 +02:00
24b0d2b8c2
setup.py: fix exclude, add example_designs to exclude
2018-07-19 11:23:52 +02:00
4edba99b38
phy: remove s6rgmii (not working correctly).
...
Alternative is to create a wrapper around the rgmii_if from Xilinx as it's done in opsis-soc
2018-07-18 10:09:01 +02:00
6b872fd271
setup.py: exclude sim, test, doc directories
2018-07-18 09:40:20 +02:00
40d91f09c4
phy: use rx_dv instead of dv
2018-07-05 10:48:17 +02:00
ba2fdc532d
README: add 1000BaseX phy
2018-06-29 14:47:22 +02:00
a2dbdd6d2b
phy: add a7_1000basex phy (from misoc)
2018-06-29 14:26:19 +02:00
95849a0fed
core/icmp: use buffered=True on buffer to allow tools to use block rams
2018-05-27 07:41:32 +02:00
33afda74f7
README: add migen dependency
2018-03-01 10:43:30 +01:00
79a6ba7709
replace litex.gen imports with migen imports
2018-02-23 13:40:09 +01:00
c15f089eba
bump to 0.2.dev
2018-02-23 13:39:53 +01:00
c42aa09878
uniformize litex cores
2018-02-22 10:12:33 +01:00
4e08d6e9f9
Merge pull request #13 from felixheld/crc_pythonize
...
pythonize CRC calculation
2018-02-22 09:00:25 +01:00
Florent Kermarrec
Vamsi K Vytla
Yehowshua Immanuel