- Improve signal names.
- Use re on memories to simplify addressing (still need to anticipate read by 1 cycle).
Also do minor cleanups to LiteEthMACSRAMWriter.
LiteX integration is already able to automatically convert bus data-width: When adding a 64-bit peripheral
to 32-bit SoC, the adapters will automatically be inserted.
When SRAM dw is 64-bit for a 32-bit SoC, automatic convertion can be seen in the build log:
INFO:SoCBusHandler:ethmac Region allocated at Origin: 0x80000000, Size: 0x00002000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:ethmac Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:ethmac added as Bus Slave.
INFO:SoCIRQHandler:ethmac IRQ allocated at Location 2.
Also fix copyright order.
Adds a wishbone.Converter between the SRAM Wishbone slave and the
wishbone.Decoder connected to the SoC bus, to support SRAM data widths
larger than the system bus Wishbone data width. This is important to
be able to run a 32-bit SoC with a 64-bit MAC data path and SRAM
storage.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
This removes various assumptions about having a 32 bit data width in
the SRAM module. Especially the last_be encoding and decoding have
been seperated into a module, which generates the one-hot encodings
and decodings on the fly.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
They aren't strictly necessary, especially since the MAC can have
a wider data path and thus cope with running slightly slower
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Otherwise we don't get the DDROutput overrides and the standalone
core fails to generate when using GMII_MII
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To support a simple GMII simulation, skip clock generation and buffer
logic. This allows to operate a GMII interface over sys_clk. Proper
GMII clocking support can still be added in the simulation, this
should work when setting model = False.
It also sets an attribute "model" such that we can avoid adding
Platform constraints in the rest of the ecosystem (such as
litex/litex/soc/integration/soc.py, add_ethernet and add_etherbone).
Signed-off-by: Leon Schuermann <leon@is.currently.online>
