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  • 7d24ac33ae version: Bump to 2024.04. 2024.04 Florent Kermarrec 2024-06-05 22:07:12 +0200
  • e209a1c697
         Merge pull request #160 from whiteb3ar/master enjoy-digital 2024-04-14 08:26:23 +0200
  • 0e8079a9da phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed Andrei Novysh 2024-04-14 00:37:31 +0300
  • a0d59dd264 frontend/stream/LiteEthStream2UDPTX: Condition source.last_be to source.last. Florent Kermarrec 2024-04-11 10:47:02 +0200
  • 79ccffcfa7 mac/crc: Revert 30e66a7 (introducing a regression). Florent Kermarrec 2024-04-08 17:15:04 +0200
  • 421e008fc8 mac/crc: Cosmetic cleanup. Florent Kermarrec 2024-04-05 09:20:28 +0200
  • fb407ce98b core/ip/LiteEthIPTX: Enable buffer to ease timings on checksum. Florent Kermarrec 2024-04-04 17:58:30 +0200
  • b5d7ba1220 core/udp: Revert TX/RX Buffer since not helping (at least for now). Florent Kermarrec 2024-04-04 17:52:43 +0200
  • 211cdc26f3 core/ip: Add optional input buffer on LiteEthIPTX to improve timings. Florent Kermarrec 2024-04-04 17:26:54 +0200
  • 30e66a7e21 mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output. Florent Kermarrec 2024-04-04 16:39:32 +0200
  • 3e8103996f mac/crc/LiteEthMACCRC32Inserter: Switch crc_packet/last_be to reset_less for timings. Florent Kermarrec 2024-04-04 16:17:36 +0200
  • b7443f5fd3 gen/mac: Allow 16-bit data_width. Florent Kermarrec 2024-04-04 13:36:16 +0200
  • c18cfb8bc0 core/arp/LiteEthARPTX: Simplify last_be generation. Florent Kermarrec 2024-04-04 13:35:57 +0200
  • d5ba0d21ef frontend/etherbone: Enable TX/RX buffer on UDP Port when requesting it (and others cosmetic cleanups). Florent Kermarrec 2024-04-04 13:09:17 +0200
  • d558122251 core/udp: Allow adding TX/RX Buffer on interface to improve/cut timings. Florent Kermarrec 2024-04-04 13:08:25 +0200
  • c250bb1485 mac/crc/LiteEthMACCRC32Inserter: Simplify crc.ce logic. Florent Kermarrec 2024-04-04 13:06:59 +0200
  • 3c1f4dbf6c phy/a7_gtp: Allow using GTGREFCLK0/1 input as reference clocks. Florent Kermarrec 2024-04-04 10:50:47 +0200
  • c1dc02093d
         Merge pull request #158 from enjoy-digital/crc_cleanup enjoy-digital 2024-03-26 12:41:30 +0100
  • bbdd6835aa mac/crc: Cleanup and try to move data-path connection outside of FSM for timings. crc_cleanup Florent Kermarrec 2024-03-26 11:55:05 +0100
  • b22ac619ab mac/crc: Avoid dummy CRC classes since we only have one CRC Engine implementation. Florent Kermarrec 2024-03-26 11:36:43 +0100
  • 95ff76867f mac/crc: Rename dw to data_width. Florent Kermarrec 2024-03-26 11:30:07 +0100
  • 01abb2a60f mac/crc/LiteEthMACCRC32: Rename last_be to be and add comments. Florent Kermarrec 2024-03-26 11:28:09 +0100
  • 5fad30cbc9 mac/crc/LiteEthMACCRC32: Simplify last_be using reset value and merge for loops. Florent Kermarrec 2024-03-26 11:07:06 +0100
  • d9f7ae4882 mac/crc: Another cleanup pass. Florent Kermarrec 2024-03-26 10:48:18 +0100
  • aded91f8cb mac/crc: Add optmize_xors method and better signal names. Florent Kermarrec 2024-03-26 10:25:22 +0100
  • 1720050729 mac/crc: Switch to LiteXModule, LiteX's Reduce and avoid OrderedDict (no longer required). Florent Kermarrec 2024-03-26 09:59:22 +0100
  • 4af0c77371 phy/a7_1000basex: Switch txoutclk buffer to BUFG. Florent Kermarrec 2024-03-25 16:00:39 +0100
  • 292551a0f1 phy/a7_1000basex: Add parameters to allow selecting TX/RX Clock Managment Modules (PLL or MMCM) and buffer types. Florent Kermarrec 2024-03-22 12:28:24 +0100
  • 60eee97b49 mac/crc.py: Implement optimized CRC checker Rowan Goemans 2024-03-21 01:44:48 +0100
  • 1a5d93509b liteeth_gen: Allow selection QPLL channel on Artix7 through qpll_channel parameter. Florent Kermarrec 2024-03-19 17:56:13 +0100
  • 5eb986b004 liteeth_gen: Allow external QPLL on Artix7 to allow multiple PHYs per Quad. Florent Kermarrec 2024-03-18 14:24:32 +0100
  • 0914fb5e51 liteeth_gen: Add optional --name parameter to configure generated verilog name. Florent Kermarrec 2024-03-18 13:46:37 +0100
  • 2c67d13456 examples: Improve identation/presentation. Florent Kermarrec 2024-03-18 13:43:11 +0100
  • c4b58ddad2
         Merge 7732e0d23c into 3061bf91ce Rowan Goemans 2024-03-06 12:56:53 -0700
  • 804f2721ec
         Merge 8740aafdf3 into 3061bf91ce Rowan Goemans 2024-03-06 12:56:53 -0700
  • a8229d9ff1
         Merge 14010b3579 into 3061bf91ce Rowan Goemans 2024-03-04 16:26:21 +0000
  • 14010b3579 core/dhcp: Add check to ensure DHCP cannot be used without IP broadcast support rowanG077 2023-09-15 09:38:55 +0200
  • fe7421b55c core/udp: Add `with_dhcp` argument and remove dhcp plumbing from core generator rowanG077 2023-09-13 14:06:42 +0200
  • d940403132 core/dhcp.py: Add options parsing core/dhcp.py: Add lease time support rowanG077 2023-09-13 13:58:21 +0200
  • e3a5d6fc19 phy/pcs_1000basex: Expose timers to ease debug. Florent Kermarrec 2024-03-04 16:19:08 +0100
  • ab4606c5a1 phy/1000basex: Expose pcs, tx_init and rx_init modules to ease debug. Florent Kermarrec 2024-03-04 16:17:39 +0100
  • 3061bf91ce liteeth_gen: Make udp_ports definition optional in .yml file (ex for configuration with only Etherbone). Florent Kermarrec 2024-02-29 14:56:52 +0100
  • 21ff1b9369 liteeth_gen: Remove unwanted data_width assertion on Etherbone. Florent Kermarrec 2024-02-29 14:49:37 +0100
  • b4e2850623 phy/Ultrascale/1000BaseX: Configure PROGDIV_CFG from linerate. Florent Kermarrec 2024-02-07 11:34:01 +0100
  • 80ba793bcf phy/Ultrascale/1000BaseX: Switch to LiteICLink's ChannelPLL for more flexibility/simplicity. Florent Kermarrec 2024-02-07 09:24:01 +0100
  • 8f521d838c liteeth_gen: Finish Artix7 2500BaseX integration. Florent Kermarrec 2024-02-06 18:26:54 +0100
  • 1fefe49e74 README: List 2500BaseX support. Florent Kermarrec 2024-01-23 15:57:00 +0100
  • dd2ecfefd8 liteeth/phy: Add USP_GTY_2500BASEX support. Florent Kermarrec 2024-01-23 15:55:25 +0100
  • fec0e23eb1 liteeth/phy: Add USP_GTH_2500BASEX support. Florent Kermarrec 2024-01-23 15:50:01 +0100
  • 664a633d29 liteeth/phy: Fix 2500basex linerate. Florent Kermarrec 2024-01-23 15:44:33 +0100
  • 4527e8137e liteeth/phy: Add KU_2500BASEX support. Florent Kermarrec 2024-01-23 15:42:01 +0100
  • 3e8dbe23ef liteeth/phy: Add K7_2500BASEX support. Florent Kermarrec 2024-01-23 15:34:10 +0100
  • 19c555171b liteeth_phy: Merge a7_2500basex in a7_1000basex and handle changes through linerate. Florent Kermarrec 2024-01-23 15:23:51 +0100
  • 5a1caed75f liteeth_gen: Add A7_2500BASEX support. Florent Kermarrec 2024-01-23 13:54:06 +0100
  • a00c9a3d22 liteeth_gen: Add TX/RX polarity support to SGMII/1000BASEX PHYs. Florent Kermarrec 2024-01-23 12:45:48 +0100
  • 3b10143da2 liteeth_gen: Fixes on Artix7 integration. Florent Kermarrec 2024-01-22 19:49:30 +0100
  • 650433dd4b phy/gw5rgmii: fix clks assignment Gwenhael Goavec-Merou 2024-01-22 06:38:16 +0100
  • 95081445e7 liteeth_gen/A7_1000BASEX: Add support for 156.25MHz refclk_freq and fix 200MHz to 125MHz. Florent Kermarrec 2024-01-19 21:40:45 +0100
  • c05de191e2 liteeth_gen: Add specific A7_1000BASEX support and example configuration. Florent Kermarrec 2024-01-18 13:27:32 +0100
  • 1ea28bd93a phy/gw5rgmii: avoid synthesis noise by adding missing in/out ports for IODELAY primitives Gwenhael Goavec-Merou 2024-01-08 07:26:35 +0100
  • 1c9acfeaa7 setup.py: Fix/Revert classifiers. Florent Kermarrec 2024-01-01 15:27:37 +0100
  • a4b74c32c1 setup.py: Bump to 2023.12 to prepare release. 2023.12 Florent Kermarrec 2023-12-25 15:34:01 +0100
  • d3a05ae631 setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguments in functions). Florent Kermarrec 2023-12-19 10:24:18 +0100
  • 6ec993650c setup.py: Specify UTF-8 encoding for long_description/README.md. Florent Kermarrec 2023-12-19 10:12:51 +0100
  • 0ae737956d setup.py: Improve indentation. Florent Kermarrec 2023-12-19 09:10:32 +0100
  • 1b09112237 core: Add buffers to IP and ICMP Rowan Goemans 2023-11-12 18:42:36 +0100
  • 4eec8419d0 test/test_model: Update EtherbonePacket. Florent Kermarrec 2023-11-10 16:14:26 +0100
  • f3f0486990 CONTRIBUTORS: Update. Florent Kermarrec 2023-11-10 10:41:51 +0100
  • fc190e8f7b
         Merge pull request #149 from trabucayre/etherbone_hybrid enjoy-digital 2023-10-23 18:33:46 +0200
  • daf1a1ac63 core/__init__: LiteEthUDPIPCore, LiteEthIPCore: expose interface & endianness at LiteEthUDPIPCore constructor. LiteEthIPCore: don't hardcode interface, pass macaddr and endianness to LiteEthMAC Gwenhael Goavec-Merou 2023-10-23 16:18:05 +0200
  • 09d31b5af8 core/arp: Fix mem_wr_port alias direction. Florent Kermarrec 2023-10-13 14:31:03 +0200
  • 9d13f612c1 core/arp: Fix missing set of response.mac_address in UPDATE_TABLE and reset update_count at the end of CLEAR state. Florent Kermarrec 2023-10-11 09:09:02 +0200
  • e784bf8fd3 core/arp: Use signals for alias to simplify debug. Florent Kermarrec 2023-10-11 09:03:19 +0200
  • 79600f954a mac/sram: Minor cleanup by directly using port instead of ports[n] in the loop. Florent Kermarrec 2023-10-10 14:55:26 +0200
  • 8b2bd00a95 mac/sram: LiteEthMACSRAMReader: force READ_FIRST for mems ports (fix tx packet corruption for efinix trion/titanium) Gwenhael Goavec-Merou 2023-10-10 14:49:36 +0200
  • 42772f4388 setup.py: Update to 2023.08. Florent Kermarrec 2023-09-18 08:42:17 +0200
  • a6775fe1af phy/efinix: Use new LiteX's ClkInput/Output abstraction to simplify code/avoid duplications. 2023.08 Florent Kermarrec 2023-09-12 09:34:43 +0200
  • 618f20b603 phy/efinix: Fix i/n conflict. Florent Kermarrec 2023-09-11 11:11:43 +0200
  • 41ad929b36 phy/efinix: Avoid manual PLL numbering and add auto-numbering for auto_eth names. Florent Kermarrec 2023-09-11 10:43:50 +0200
  • 44f739afe2 phy/trionrgmii: Update from titaniumrgmii (untested). Florent Kermarrec 2023-09-07 14:24:04 +0200
  • 3a617034dc phy/titaniumrgmii: Simplify and fix, now working on Ti60F225 dev kit + RGMII adapter. Florent Kermarrec 2023-09-07 13:49:05 +0200
  • 28fc02bb30 core/dhcp: Minor review/cleanup. Remove comment on counter optimization since does not seems to be implemented. Florent Kermarrec 2023-09-03 19:44:49 +0200
  • 936b6348e5
         Merge pull request #145 from rowanG077/dhcp/tx-opt enjoy-digital 2023-09-03 19:32:09 +0200
  • f0a905c815 core/dhcp.py: tx FSM optimizations rowanG077 2023-08-30 13:10:36 +0200
  • b491d5078c phy/a7_2500basex: Update copyright/minor cleanup. Florent Kermarrec 2023-09-01 12:56:20 +0200
  • 42c7e0eea2
         Merge pull request #143 from Icenowy/gw5rgmii enjoy-digital 2023-09-01 12:13:57 +0200
  • da3c69c0b5
         Merge pull request #146 from cyntem/master enjoy-digital 2023-09-01 12:11:30 +0200
  • 9a904fb8dc Artix 7 2500BASE-X Sergey Razumov 2023-08-31 11:00:01 +0300
  • 23035e7c63 phy/rmii: merging cd_eth_rx, cd_eth_tx and clock pads when refclk_cd is None Gwenhael Goavec-Merou 2023-08-30 19:46:26 +0200
  • 0f055b1c0f phy/efinix: IO exclusion on DDROutput/Input now directly done in LiteX. Florent Kermarrec 2023-08-30 18:09:41 +0200
  • 8436d775f6 phy/efinix: Switch to new DDROutput/Input now supported in LiteX for Efinix. Florent Kermarrec 2023-08-30 11:30:29 +0200
  • b201aeb083 phy/efinix: Directly exclude IOs when primitive is used, avoid having to do it in user design. Florent Kermarrec 2023-08-30 08:54:46 +0200
  • ab93bc8ed1 phy: add initial GW5RGMII (RGMII for Gowin Arora V series) Icenowy Zheng 2023-08-15 11:10:28 +0800
  • f0c876ca77 core/arp: Only increment clear_timer in IDLE state and change timeout to 1s. Florent Kermarrec 2023-08-02 14:54:32 +0200
  • cb1e1932b3 global: Use new WaitTimer integrated cast to int. Florent Kermarrec 2023-08-01 14:42:16 +0200
  • 16224432d9
         Merge pull request #142 from enjoy-digital/arp_table enjoy-digital 2023-07-31 18:03:25 +0200
  • ea45c8704f core/arp: Add enable signals for Cache/Clear for optional external control. arp_table Florent Kermarrec 2023-07-31 17:26:58 +0200
  • c5b53326bb core/arp: Add clear timer to clear cache periodically and minor cleanups. Florent Kermarrec 2023-07-31 16:57:42 +0200
  • b74618d1ed core/arp: Switch LiteEthARPCache to a proper Memory and allow multiple entries. Florent Kermarrec 2023-07-31 16:15:10 +0200
  • dc7ed0de6f core/arp: Move ARP cache logic to LiteEthARPCache and define interfaces. Florent Kermarrec 2023-07-31 14:46:16 +0200