Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
913 Commits 9 Branches 14 Tags 11 MiB
Commit Graph

913 Commits

Author SHA1 Message Date
Florent Kermarrec c96e7c8fb9 platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv 2019-12-31 18:07:18 +01:00
Florent Kermarrec 2259042383 pipistrello: add copyrights 2019-12-31 17:44:24 +01:00
enjoy-digital 6324433e1c
Merge pull request #28 from zakgi/master 
Adding initial support for Saanlima's Pipistrello LX45 board
 2019-12-31 17:33:25 +01:00
Florent Kermarrec 980b0ebda0 targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer) 2019-12-31 17:30:23 +01:00
Florent Kermarrec 10e5248bda targets/de10lite: minor cleanup on import/_CRG 2019-12-31 17:26:09 +01:00
enjoy-digital 9d6a6c1bcb
Merge pull request #29 from msloniewski/master 
Update de10lite platform
 2019-12-31 17:17:48 +01:00
msloniewski 9c5a4f757f targets/de10lite: add VideoSoC with VGA peripheral 
Add VideoSoC build option, based on Frank Buss example.
 2019-12-30 23:25:43 +01:00
msloniewski cace17e162 targets/de10lite: refactor setting up clock domains 
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
 2019-12-30 23:25:43 +01:00
msloniewski 9ed68d129f platforms/de10lite: add additional configuration 
Use single image with memory initialization
to make more space for SoC ROM sector.
 2019-12-30 23:23:44 +01:00
msloniewski 28753a2c04 platforms/de10lite: remove UART pins from GPIO resource 
V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
 2019-12-30 23:06:58 +01:00
Tim 'mithro' Ansell 359918c2a2 Comment out template overrides for now. 2019-12-30 19:23:05 +01:00
Florent Kermarrec 1f32dcf662 partner: rename orange_crab to orangecrab 2019-12-30 12:07:34 +01:00
Florent Kermarrec 8965b01347 partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC 2019-12-30 11:54:53 +01:00
Greg Davill e77afaaef0 partner: add OrangeCrab support (https://github.com/gregdavill/OrangeCrab) 2019-12-30 11:54:45 +01:00
Giammarco Zacheo 39e428581f Adding initial support for Saanlima's Pipistrello LX45 board 2019-12-29 18:29:11 -08:00
Florent Kermarrec 48476be9e2 aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address 2019-12-14 22:10:04 +01:00
Florent Kermarrec 7184032555 aller/neired/tagus: fix gateware/software build directory 2019-12-14 11:29:15 +01:00
enjoy-digital c49693fdf3
Merge pull request #24 from dkozel/fix_numato_csr_headers 
Fix numato csr headers
 2019-12-14 11:23:09 +01:00
Derek Kozel 4334ba9527 partner/aller, nereid, tagus: Remove deprecated param 
get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
 2019-12-14 01:04:28 +00:00
Derek Kozel 3012cf75fe partner/aller, nereid, tagus: Use updated csr APIs 
litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
 2019-12-14 01:00:52 +00:00
Florent Kermarrec d91458c3e6 targets/versa_ecp5: fix compilation with diamond 2019-12-06 16:16:19 +01:00
Florent Kermarrec 30ea463b41 targets: keep attributes are no longer needed since automatically added when applying constraints to signals. 2019-12-06 16:01:59 +01:00
Florent Kermarrec 8fa3f09226 partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices. 2019-12-06 15:22:40 +01:00
Florent Kermarrec 0a56d86b1a partner/c10lprefkit: remove FAMILY platform_command (not needed) 2019-12-06 15:21:48 +01:00
Florent Kermarrec 5193f7155a partner/aller,nereid & tagus: fix compilation 2019-12-03 09:37:18 +01:00
Florent Kermarrec f7fbfb4639 partner/community/targets: uniformize, improve presentation 2019-12-03 09:33:08 +01:00
Florent Kermarrec 1b1370d086 official/targets: uniformize, improve presentation 2019-12-03 09:07:09 +01:00
Sean Cross 4e13b7fdab targets: fomu: move SoCCore import definition 
The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
626533ce9d

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-25 12:46:21 +08:00
Sean Cross 0da263fa75 platforms: fomu: add spiflash4x definition 
Fomu Hacker supports dual spi, so add a "spiflash4x" definition.
The litex spi_flash module will run this flash in dual mode, because the
`dq` array is only two signals wide.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-24 21:56:57 +08:00
Sean Cross 45b847b466 fomu: add documentation to crg 
This documentation can be fetched using a package such as lxsocdoc.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-23 12:55:26 +08:00
Sean Cross 2c82e02df9 fomu: pvt: swap miso and mosi 
These pins were swapped in the definition, which made them not work so
well.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-22 18:57:26 +08:00
Florent Kermarrec 4231d59901 platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling) 2019-11-16 09:40:30 +01:00
Florent Kermarrec 2a0fbcadd2 ac701: add pcie_x1 pins 2019-11-06 09:29:55 +01:00
Florent Kermarrec 5bd8c4d74f targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build) 2019-11-01 10:52:56 +01:00
Florent Kermarrec 1ae26dd499 targets: use type="io" instead of io_region=True 2019-10-30 16:35:32 +01:00
enjoy-digital 05a0d5fa3d
Merge pull request #21 from gsomlo/gls-sync-litex 
Gls sync litex
 2019-10-30 09:47:55 +01:00
Gabriel Somlo 8878c0a84a versa_ecp5, trellisboard: add trellis toolchain specific arguments 
Sync up with Litex commit #49372852d.
 2019-10-29 12:32:41 -04:00
Gabriel Somlo 5f80633154 targets: increase integrated ROM size if EthernetSoC used 
Sync up with litex commit #201218b2c.
 2019-10-29 12:32:41 -04:00
Gabriel Somlo c83e10d9f3 official/platforms/versa_ecp5: add serdes refclk/sma 
Sync up with litex commit #ae9c25b74.
 2019-10-29 12:32:41 -04:00
Florent Kermarrec 91083f99a8 ulx3s: simplify SDRAM module selection 2019-10-13 21:15:22 +02:00
enjoy-digital 6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target 
memory device selection for ulx3s
 2019-10-13 20:59:16 +02:00
Steven Osborn abf6f7b09a memory device selection for ulx3s 2019-10-13 09:27:33 -07:00
enjoy-digital 53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target 
add sys clock freq flag, uses same method as current versa code
 2019-10-13 10:32:43 +02:00
Steven Osborn 34507eb431 add sys clock freq flag, uses same method as current versa code 2019-10-13 00:44:07 -07:00
Sean Cross 92cfd629df partners: fomu-evt: add "dbg" connector 
This connector is for the six "debug" pins on the Raspberry Pi header.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-11 21:39:19 +08:00
Sean Cross 09a55d20c1 partners: fomu-evt: fix spiflash4x pin mapping 
The D3 and D4 pins were swapped around, leading to interesting issues.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-11 21:38:50 +08:00
Florent Kermarrec 785909ac5f targets: switch from shadow_base to io_regions 2019-10-09 11:09:59 +02:00
Sean Cross 19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates 
Fomu cpu updates
 2019-09-27 16:55:27 +08:00
Sean Cross c20c489d66 fomu-evt: add i2c pins 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-27 11:26:23 +08:00
Florent Kermarrec 48cd1208df targets: sync with litex targets 2019-09-25 14:09:25 +02:00