32f507cc08
Merge pull request #406 from chmousset/fix/icebreaker_bitsy
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[fix] instanciate PLL for valentyUSB
2022-06-29 10:31:42 +02:00
190f272c14
targets/sipeed_tang_primer_20k: Update build.
2022-06-29 10:00:47 +02:00
9f5ca1b1d6
test/test_targets: Add --build to generate files.
2022-06-29 09:41:57 +02:00
b61c471058
targets/avnect_aesku040: Update build.
2022-06-29 09:41:18 +02:00
d3597dea21
[fix] instanciate PLL for valentyUSB
2022-06-28 21:17:02 +02:00
6b02ea024a
ti60_f225_dev_kit: Fix ethernet build and enable debug. Now needs testing.
2022-06-28 19:54:00 +02:00
1a71932599
ti60_f225_dev_kit: Switch to Titanium RGMII PHY.
2022-06-27 19:47:22 +02:00
c14611b07c
ti60_f225_dev_kit: Add dummy 0 pin to connectors to use schematic numbering (1-40).
2022-06-27 19:47:19 +02:00
5bd2c1e7b5
Merge pull request #404 from antmicro/basys3-fix
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target: basys3: Remove redundant sdcard additions
2022-06-27 18:14:09 +02:00
46ddc36b3c
target: basys3: Remove redundand sdcard additions
2022-06-27 14:34:49 +02:00
f8ac2acffc
Merge pull request #402 from trabucayre/honour_icestorm_toolchain_args
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honours lattice toolchain args
2022-06-23 12:15:14 +02:00
eadea43fa1
honours lattice toolchain args
2022-06-22 21:05:35 +02:00
358a641317
Merge pull request #401 from antmicro/move_to_f4pga
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Move from deprecated Symbiflow to F4PGA
2022-06-20 11:56:51 +02:00
1ad2022138
quicklogic_quickfeather: Move from deprecated Symbiflow to F4PGA
2022-06-17 17:00:48 +02:00
29b72fac7e
taobao_a_e115fb: Minor cleanups.
2022-06-15 11:55:22 +02:00
0ae1417eb5
a_e115fb: Add taobao prefix (Similar to what we do on aliexpress's boards from unknown vendors).
2022-06-15 11:53:11 +02:00
4e0e381f47
Merge pull request #398 from Icenowy/a-e115fb
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a_e115fb: new board
2022-06-15 11:37:36 +02:00
13fbcbb159
a_e115fb: new board
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It's a core board with EP4CE115 by a random vendor on Taobao.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 23:13:29 +08:00
e02bee4265
efinix_ti60_f225: Prepare 1Gbps Ethernet support through RGMII extension board.
2022-06-13 16:02:26 +02:00
c420429a3c
efinix_ti60_f225: Add the 3 QSE connectors and add RGMII Ethernet QSE extension board.
2022-06-13 16:01:28 +02:00
b32969c29f
targets/Ultrascale(+): Remove BUFGCE name overrides.
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Not required, was only useful on a specific project.
2022-06-10 19:21:04 +02:00
4a22f6bf17
targets/avnet_aesku40: Fix compilation and minor cleanups.
2022-06-07 13:08:02 +02:00
d37af4aece
Merge pull request #395 from AEW2015/master
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Support for "discontinued" Avnet aes-ku040-db-g development board
2022-06-07 12:13:47 +02:00
313e758ffe
Updated copywrite and renamed to avnet_aesku40
2022-06-03 20:49:52 -06:00
5188b17a71
sipeed_tang_nano_9k: Switch to old HyperRAM core until issue with new one is investigated. Also do some cleanup and disable video_terminal by default.
2022-06-03 12:28:38 +02:00
ddc6140e25
sipeed_tang_primer_20k: Swithc to GW2APLL.
2022-06-03 12:01:49 +02:00
6e33d9249f
sipeed_tang_primer_20k: Cleanup/Fix.
2022-06-03 11:40:10 +02:00
68733c6e92
Merge pull request #396 from Icenowy/tang20k
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sipeed_tang_primer_20k: new board
2022-06-03 10:14:55 +02:00
b97d9cd9e8
sipeed_tang_primer_20k: new board
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Only initial support is added.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-03 00:24:20 +08:00
4d98dd38a7
Merge branch 'litex-hub:master' into master
2022-06-01 23:01:43 -06:00
1b96067113
added aesku40 dev board
2022-06-01 22:54:03 -06:00
48353735fa
Merge pull request #393 from swetland/ethernet
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muselab icesugar pro: add ethernet/etherbone support
2022-05-20 22:10:02 +02:00
28c2803ee9
Merge pull request #392 from hansfbaier/enclustra-mercury-fixes
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enclustra_mercury_kx2: add clk100, leds, base board serial, DDR3 termination
2022-05-20 22:09:23 +02:00
5a714167ed
muselab icesugar pro: add ethernet/etherbone support
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- use P4 header for a waveshare ethernet phy module
- add --with-ethernet, --with-etherbone, --eth-ip, and --eth-dynamic-ip
target configuration options
2022-05-19 14:46:09 -07:00
2214c7baec
enclustra_mercury_kx2: remove useless clk100, because it is not connected to a clock pin
2022-05-20 04:42:06 +07:00
f1e021cbbe
enclustra_mercury_kx2: add clk100, leds, base board serial, DDR3 termination, DDR3 voltage setting
2022-05-19 15:41:44 +07:00
64773b4085
Merge pull request #390 from hansfbaier/hpc-xc7k420t
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HPC Store xc7k420t
2022-05-16 11:20:15 +02:00
df5b38df68
Merge pull request #391 from minexo79/master
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Move HDMI Support From Sipeed Tang Nano 4K.
2022-05-16 11:18:37 +02:00
f14865fa42
Merge branch 'hpc-xc7k420t' of github.com:hansfbaier/litex-boards into hpc-xc7k420t
2022-05-16 12:34:30 +07:00
c5d292c7f9
Get 4 DDR modules working with Vivado
2022-05-16 12:33:04 +07:00
efa5740811
Move HDMI Support From Sipeed Tang Nano 4K.
2022-05-15 10:53:09 +08:00
26c0f546c7
Merge branch 'litex-hub:master' into hpc-xc7k420t
2022-05-14 21:40:12 +07:00
006b54e7ea
Get 3 DDR modules working with Vivado
2022-05-14 21:38:25 +07:00
1e77c28ed0
muselab_icesugar_pro/VideoHDMIPHY: Remove obsolete drive_both.
2022-05-12 16:09:40 +02:00
ee58e5dbc7
Merge pull request #388 from swetland/hdmi
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muselab: icesugarpro: fix HDMI output
2022-05-12 15:09:03 +02:00
dabf2cff06
sqrl_acorn: Switch back to PCIe Gen2 X4 and enable 64-bit addressing (Not really useful except for 64-bit addressing tests).
2022-05-12 13:32:41 +02:00
f383ad3938
Support HPC Store XC7K420T board
2022-05-12 12:55:46 +07:00
d1096a2cd0
Add HPC Store XC7K420T board
2022-05-11 08:58:50 +07:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
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Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
0ce7f8354c
Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
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python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
2022-05-03 19:04:06 +02:00
enjoy-digital
Charles-Henri Mousset
Robert Szczepanski
Gwenhael Goavec-Merou
Icenowy Zheng
AEW2015
Brian Swetland
Hans Baier
minexo79