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261 Commits

Author SHA1 Message Date
Florent Kermarrec 9baa9d5d83 platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811). 2021-02-12 15:23:17 +01:00
Michael Betz 7442c2dada vc707.py: clk156 add missing constraint 2021-02-08 19:04:01 -08:00
Florent Kermarrec fef9dd036a platforms/de0nano: directly use JP1 connector for serial pins. 2021-02-08 09:52:26 +01:00
enjoy-digital ea58ef94a7
Merge pull request #170 from hansfbaier/master 
arrow_sockit: add support for MiSTer XS SDRAM modules
 2021-02-04 16:44:58 +01:00
Jan Kowalewski cdff5e3ca3 nexys_video: enable symbiflow toolchain 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-02-03 14:52:54 +01:00
Hans Baier c64e13f687 arrow_sockit: add support for MiSTer XS SDRAM modules 2021-02-03 09:37:03 +07:00
Florent Kermarrec 7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. 
./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>
 2021-02-01 13:32:01 +01:00
Florent Kermarrec 6cce07d9db tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios. 2021-02-01 13:31:44 +01:00
Florent Kermarrec 0831b33285 tec0117: fix copyrights. 2021-02-01 13:31:39 +01:00
Hans Baier 5e4b29c0b5 sockit: Fix cable name, default to jtag_atlantic 2021-02-01 11:48:06 +07:00
enjoy-digital 601c297c8f
Merge pull request #164 from rdolbeau/ztex213 
Support file for the ZTEX USB-FPGA Module 2.13
 2021-01-30 21:43:07 +01:00
Guillaume REMBERT 31df53ef0a Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work) 2021-01-30 13:19:08 +01:00
Romain Dolbeau 027e57b851 Support file for the ZTEX USB-FPGA Module 2.13 2021-01-30 05:19:18 -05:00
Florent Kermarrec abccd12058 tec0117: add initial SDRAM support for the embedded SDRAM of the SIP. 
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
 2021-01-29 22:28:40 +01:00
Vadzim Dambrouski 345feddce9 ECPIX-5: ddram: Add missing address pin. 
Fixes #161
 2021-01-29 16:03:43 +03:00
Florent Kermarrec 7525b8772f platforms/fpc_iii: avoid dummy pin on ethernet.rst_n. 
rst_n is optional in LiteEth's PHYs.
 2021-01-29 09:33:33 +01:00
Florent Kermarrec 19767e1a2a platforms/fpc_iii: avoid using dummy pin on odt. 
Now possible with 2f5784432d.
 2021-01-29 09:30:54 +01:00
Florent Kermarrec 6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00
Gary Wong 4e5bb1bf1e Add FPC-III board support. 
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
 2021-01-28 09:51:42 -07:00
Florent Kermarrec aa20fca1f1 ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3. 2021-01-28 14:25:16 +01:00
enjoy-digital 691bfd8b70
Merge pull request #159 from euryecetelecom/master 
Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
 2021-01-28 14:01:01 +01:00
Alessandro Comodi bd716d956f netv2: add device variant to allow 100T as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-28 13:19:53 +01:00
Guillaume REMBERT 9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Kaz Kojima c3fa0eac8b Add colorlight i5 board support 2021-01-27 11:44:59 +09:00
Florent Kermarrec 537f494cbb arrow_sockit: review/harmonize with others boards. 2021-01-25 09:14:46 +01:00
Florent Kermarrec 4adc1b14c4 platforms/de0nano: use separator for connectors. 2021-01-25 08:58:12 +01:00
enjoy-digital bbaa2fdc98
Merge pull request #149 from hansfbaier/master 
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
 2021-01-25 08:55:48 +01:00
enjoy-digital 45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash 
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
 2021-01-24 21:22:35 +01:00
enjoy-digital 8132f9f65b
Merge pull request #154 from euryecetelecom/master 
Fix SDCard issue when no SDCard inserted in ECPIX5 board.
 2021-01-24 21:14:58 +01:00
Blake Smith cae51c0c24 ULX3S: Make spiflash optionally accessible from the SoC, and bootable 2021-01-23 14:44:26 -06:00
Hans Baier aa771e9ff4 de0-nano: add connectors 2021-01-23 20:18:15 +07:00
Hans Baier c9f0745d54 sockit: add board definitions for Terasic SocKit 2021-01-23 20:17:38 +07:00
Guillaume REMBERT b386ee5059 Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence. 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
 2021-01-20 18:02:13 +01:00
Vadim Kaushan a678672fc9
ecpix5: add option to select ECP5 device 2021-01-19 01:22:52 +03:00
enjoy-digital a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard 
genesys2: LiteSDCard support
 2021-01-07 08:12:24 +01:00
Gabriel Somlo 4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:10:13 -05:00
Geert Uytterhoeven 4a95b94dbf platforms/ecp5: Fix slewrate configuration 
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2021-01-04 17:08:51 +01:00
Florent Kermarrec 93779ecb95 platforms/colorlight_5a_75b: revert toolchain args. 
Useful to do tests with Diamiond.
 2020-12-29 14:22:42 +01:00
enjoy-digital f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0 
add colorlight v8.0 PCB
 2020-12-29 14:20:29 +01:00
Florent Kermarrec b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m 3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Shinken Sanada 4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec 9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
Sahaj Sarup 2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal 
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
 2020-12-23 02:24:18 +05:30
Florent Kermarrec ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout. 
DDR4 now validated successfully with LiteDRAM on the 4 channels.
 2020-12-11 13:58:26 +01:00
Robert Winkler 18337cdf25 targets/arty: sync with litex repository 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-12-07 17:32:40 +01:00
Alessandro Comodi f66860c201 zybo_z7: fix clock pin constraint 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-12-07 16:46:20 +01:00
Gwenhael Goavec-Merou 8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00
David Shah 11fa5c34ac nexus: Allow selection of toolchain 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-25 09:45:25 +00:00
Nathaniel R. Lewis 389b623fe2 targets/litefury: new target 
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury
 2020-11-19 21:52:14 -08:00