c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
23760e2eae
orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC).
2021-01-22 22:55:02 +01:00
b386ee5059
Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence.
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
2021-01-20 18:02:13 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
e71a4940c0
nexys4ddr: etherbone support
2021-01-15 12:14:40 -05:00
6a5f2f59a6
targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands.
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This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.
Also remove un-needed cd_sys2x_eb.
2021-01-12 18:57:22 +01:00
9ff90eb9fe
targets/c10lprefkit: fix default sys-clk-freq.
2021-01-12 16:15:52 +01:00
0a7443d273
targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1.
2021-01-08 19:30:37 +01:00
ae5494d7b6
orangecrab: defaults to USB-ACM UART.
2021-01-08 19:01:41 +01:00
c6e75122d9
sds1104xe: defaults to Crossover UART.
2021-01-08 19:00:41 +01:00
ab72f69937
targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
2021-01-08 18:50:01 +01:00
0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
869cce2bba
targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.
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eth-ip will also be used to configure Ethernet IP addresss.
2021-01-07 09:26:38 +01:00
c829a47c31
targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used.
2021-01-07 09:17:28 +01:00
adbcc81ecf
Merge pull request #145 from hansfbaier/master
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colorlight: Add option for etherbone ip address and LED chaser
2021-01-07 09:08:43 +01:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
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genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
d2d17e00a2
Merge pull request #142 from geertu/master
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platforms/ecp5: Fix slewrate configuration
2021-01-07 08:11:30 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
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The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
0d69cfa6b0
colorlight: make LEDs optional
2021-01-05 08:03:26 +07:00
4bec17e1a7
colorlight: Add option for etherbone ip address
2021-01-05 07:49:44 +07:00
2589d9f704
genesys2: add (spi-)sdcard build options
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:57:21 -05:00
4eb0026a69
genesys2: add "rst" and "cd" signals to (spi-)sdcard records
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:10:13 -05:00
4a95b94dbf
platforms/ecp5: Fix slewrate configuration
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When building linux-on-litex-vexriscv for OrangeCrab:
Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)
Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW". Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-01-04 17:08:51 +01:00
fe67766fb7
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
2021-01-04 11:38:07 +01:00
0e3c03f2f6
mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0).
2021-01-04 10:48:34 +01:00
5cc49bafbd
orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).
2021-01-04 09:42:05 +01:00
1fb24d4c71
orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset.
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Allows the USB-ACM link to stay up during reset.
2021-01-04 09:05:19 +01:00
06cb49af37
targets/arty: add variant support through --variant args.
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./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
2020-12-29 18:43:14 +01:00
02a81d54e2
targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
2020-12-29 16:01:12 +01:00
93779ecb95
platforms/colorlight_5a_75b: revert toolchain args.
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Useful to do tests with Diamiond.
2020-12-29 14:22:42 +01:00
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0
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add colorlight v8.0 PCB
2020-12-29 14:20:29 +01:00
84098d2de5
targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133 .
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Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
2020-12-29 14:13:11 +01:00
b67b18caad
qmtech_wukong: review/cleanup platform.
2020-12-29 14:10:49 +01:00
3e6b934961
add colorlight v8.0 PCB
2020-12-29 13:52:13 +01:00
e380f24655
targets/qmtech_wukong: +x.
2020-12-29 13:24:41 +01:00
4b721eded7
add QmTech Wukong board support.
2020-12-29 13:20:42 +01:00
9beaf25822
nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.
2020-12-24 10:15:29 +01:00
2a04c5c74e
nexys4ddr: add support for litexvideo VGA Terminal
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This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.
The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
f6a106cdf4
Fix orangecrab target
2020-12-20 01:07:43 +03:00
00fc2c5166
targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.
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Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
2020-12-16 11:52:58 +01:00
bb58258fd4
Fix de10nano target
2020-12-14 15:27:33 +03:00
ec4ccc9fa5
platforms/xcu1525: fix ddram 1/2/3 pinout.
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DDR4 now validated successfully with LiteDRAM on the 4 channels.
2020-12-11 13:58:26 +01:00
519f9449fa
targets/sds1104: litex_term now directly supports crossover uart.
2020-12-10 13:56:01 +01:00
18337cdf25
targets/arty: sync with litex repository
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
f66860c201
zybo_z7: fix clock pin constraint
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-12-07 16:46:20 +01:00
8e5f955e4e
targets/orangecrab: Fix --sdram-device help text
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Obviously --sdram-device takes the SDRAM device, not the ECP5 FPGA
device.
Fixes: bf3c9dc9bf
2020-12-04 14:34:01 +01:00
fe563baec7
targets/fomu: modification to ValentyUSB no longer required.
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Following commits make it generic/portable while still using IOBuffers:
77b9d01058371526e432
2020-11-27 19:40:45 +01:00
5a4e28d47d
target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).
2020-11-27 18:53:45 +01:00
8d1095224f
add support for redpitaya14/16
2020-11-26 06:54:11 +01:00
11fa5c34ac
nexus: Allow selection of toolchain
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Signed-off-by: David Shah <dave@ds0.me>
2020-11-25 09:45:25 +00:00
159a0c751c
targets/colorlight_5a_75x: update instructions and LiteEthPHYRGMII's tx_delay (required with LiteEth fixes).
2020-11-23 12:30:36 +01:00
03bb929f27
colorlight_5a_75x: add LedChaser.
2020-11-23 10:14:20 +01:00
d18deef10d
colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2).
2020-11-23 10:13:57 +01:00
ce38cff41d
mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling
2020-11-20 15:31:47 +01:00
a2f3add24e
Merge pull request #123 from teknoman117/litefury
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Support for the RHS Research LiteFury
2020-11-20 08:44:27 +01:00
389b623fe2
targets/litefury: new target
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LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
2020-11-19 21:52:14 -08:00
49e1c34dfd
targets/acorn_cle_215: add SATA.
2020-11-18 19:14:18 +01:00
778ce53865
targets/xcu1525: add SATA.
2020-11-17 15:27:42 +01:00
27e19644f4
targets/kcu105: add SATA.
2020-11-16 18:44:18 +01:00
27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
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Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
72afb95329
targets: create platform on BaseSoC for all targets (consitency).
2020-11-12 16:57:31 +01:00
843e724e3d
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
2020-11-12 16:39:42 +01:00
9f11bfb0d1
qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets.
2020-11-12 14:33:45 +01:00
31eb74dc2d
Merge pull request #122 from baselsayeh/master
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add Qmtech EP4CE15 coreboard support
2020-11-12 14:27:49 +01:00
46e8a957fe
platforms/zybo_z7: fix default_clk typo.
2020-11-12 14:26:36 +01:00
ac075f18c7
platforms/crosslink_nx_evn/vip: add default_clk.
2020-11-12 14:26:17 +01:00
f3ccd140c2
targets/simple: add try/except on leds.
2020-11-12 14:26:00 +01:00
0fc67ddfdb
update copyright
2020-11-12 15:25:39 +02:00
7c6df67739
targets: add tinyfpga_bx target (based on icebreaker/fomu targets).
2020-11-12 14:09:25 +01:00
302e4ffdff
targets/simple: simplify (only keep minimal SoC + Leds) and add load argument.
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ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
2020-11-12 13:54:30 +01:00
a4d05522d4
platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40).
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Required to simplify simple.py target and use trellis/icestorm as default toolchain.
2020-11-12 13:33:30 +01:00
5cf7731f37
targets/netv2: add PCIe.
2020-11-12 12:16:01 +01:00
7a9f175450
targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
2020-11-12 12:08:20 +01:00
4401fec1e6
targets: remove add_csr("crg") (no longer needed).
2020-11-12 11:54:11 +01:00
bd4e92ad13
targets: cleanup, uniformize build arguments between targets.
2020-11-12 11:46:00 +01:00
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support
2020-11-12 01:56:36 +02:00
5fbb176c2a
targets/crosslink_nx: update NXLRAM import.
2020-11-09 11:05:18 +01:00
afe44e2bd6
targets/crosslink_nx_evn: update NXPLL import.
2020-11-09 10:25:30 +01:00
39d979a9d3
targets/Ultrascale: add missing AsyncResetSynchronizer import.
2020-11-09 10:25:05 +01:00
97b64d16a6
Lattice NX PLL Support
2020-11-08 20:34:46 -06:00
1f52fbaca6
xcu1525: fix last ddram channel numbering.
2020-11-06 10:48:26 +01:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
aa6b9cab4a
targets/crosslink_nx_vip: +x.
2020-11-04 09:30:57 +01:00
ce14775dfb
targets/tec0117: move SerialFlashManager import to flash function.
2020-11-04 09:30:31 +01:00
2da4eabffe
platforms/icebreaker: fix refactoring typo.
2020-11-04 09:30:01 +01:00
c093d0d0fc
platforms: cleanup pass to uniformize comments/separators/orders.
2020-11-03 10:48:57 +01:00
8d26c241cd
kc705: revert sys_clk_freq to 125MHz.
2020-11-02 19:51:48 +01:00
babf638c2b
targets/nexys_video: add SATA support.
2020-11-02 19:43:25 +01:00
d1c9cc7553
Add LFE5U-12F device for ULX3S
2020-11-01 23:45:32 +00:00
e950a4a588
targets/kc705: update sata pads.
2020-10-30 17:12:59 +01:00
a410e447e1
targets/kc705/sata: enable write support.
2020-10-30 14:51:40 +01:00
d626861e95
platforms/acorn_cle_215: add serial_io (on P2).
2020-10-29 12:10:12 +01:00
f9252fdd45
targets/kc705: simplify SATA using LiteX's add_sata integration method.
2020-10-29 10:16:40 +01:00
7da8628fba
targets/kc705: switch SATA to gen2.
2020-10-28 19:09:30 +01:00
931f6667ac
targets/kc705: add initial SATA support.
2020-10-26 15:15:24 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
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Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
Hans Baier
Florent Kermarrec
Guillaume REMBERT
Vadim Kaushan
Gabriel Somlo
Geert Uytterhoeven
la6m
Shinken Sanada
Sahaj Sarup
Robert Winkler
Alessandro Comodi
Gwenhael Goavec-Merou
David Shah
Jędrzej Boczar
Nathaniel R. Lewis
Basel Sayeh
davidcorrigan714
Kevin Mehall