Commit Graph

30 Commits

Author SHA1 Message Date
Florent Kermarrec 45494f60e0 targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
Florent Kermarrec 877bc4b45e targets: Use full imports (vendor_board). 2022-05-02 12:55:11 +02:00
Florent Kermarrec 88f2625c3d targets: Fix typos. 2022-04-21 12:29:54 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
Florent Kermarrec 00ff61baa9 targets: Simplify clock domains and remove useless reset_less.
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser.
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Florent Kermarrec d9b77c6f25 digilent_arty: Add --flash support. 2022-02-09 17:51:56 +01:00
Florent Kermarrec 621d45cd9e digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code.
sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.
2022-01-24 19:16:07 +01:00
Victor Suarez Rovere db77ea5c7a Add tweaks to Arty board to support yosys+nextpnr toolchain 2022-01-24 02:06:34 -03:00
Florent Kermarrec fccb952c4b target: Remove ident_version=True no longer required. 2022-01-18 17:13:02 +01:00
Florent Kermarrec 7114911cea targets: --no-ident-version is now directly provided by LiteX, remove it on targets implementing it. 2022-01-18 16:47:38 +01:00
Florent Kermarrec 16171282c8 digilent_arty/CRG: Add with_rst parameter to be able to easily disable rst.
On Arty, cpu_rst pin is connected to a button but also to USB-UART which also
resets the SoC when USB-UART is connected which is in some case not wanted.

with_rst provides an easy way to disable rst by setting it to False.
2022-01-07 14:12:28 +01:00
Florent Kermarrec 53dc00eab7 targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
Florent Kermarrec 68fb163a27 targets: Remove spiflash mapping on targets where it's no longer useful. 2021-09-14 18:35:13 +02:00
Florent Kermarrec 7fa22a494b arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
2021-09-07 15:07:59 +02:00
Florent Kermarrec b017a33f2b targets: Fix SPI Flash mapping on target supporting --with-spi-flash. 2021-08-23 18:05:40 +02:00
Florent Kermarrec 4e2b596ab3 digilent_arty/qmtech_xc7a35t: Rename --with-mapped-flash to --with-spi-flash. 2021-07-28 11:21:51 +02:00
Florent Kermarrec b3e7dbfd30 qmtech_xc7a35t: LiteSPI integration now provided by LiteX. 2021-07-27 19:39:50 +02:00
Florent Kermarrec 1c52e6b8fb targets/digilent_arty/spiflash: LiteSPI integration now provided by LiteX. 2021-07-27 19:30:38 +02:00
Florent Kermarrec a3f479837c digilent_arty: Allow exposing raw PMOD IOs (for tests with MicroPython). 2021-07-21 13:50:12 +02:00
Joey Bushagour 1920db3535 Add with_led_chaser argument to constructor of boards using LedChaser submodule. 2021-07-06 16:39:37 -05:00
Florent Kermarrec 7442639a5e targets/digilent_arty: Add default value for CRG's with_mapped_flash.
Otherwise break retro-compat on external design importing CRG without passing this new parameter.
2021-07-02 09:33:06 +02:00
Florent Kermarrec 5bfeb999e4 targets/digilent_arty/flash: Simplify, use Quad mode and sys_clk (fast enough ~5MB/s). 2021-04-26 16:30:35 +02:00
Karol Gugala 2854df5028 Arty: move spiflash PHY do 4x faster clk domain
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:36 +02:00
Karol Gugala 84ae2b2bbc arty: add option to use litespi QSPI controller
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:30 +02:00
Florent Kermarrec 1ca8ef97a1 targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM). 2021-03-29 16:03:19 +02:00
Florent Kermarrec ba01776432 targets/add_sdram: Simplify call by removing useless arguments.
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
Florent Kermarrec 8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00