d91458c3e6
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:16:19 +01:00
30ea463b41
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 16:01:59 +01:00
8fa3f09226
partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices.
2019-12-06 15:22:40 +01:00
0a56d86b1a
partner/c10lprefkit: remove FAMILY platform_command (not needed)
2019-12-06 15:21:48 +01:00
5193f7155a
partner/aller,nereid & tagus: fix compilation
2019-12-03 09:37:18 +01:00
f7fbfb4639
partner/community/targets: uniformize, improve presentation
2019-12-03 09:33:08 +01:00
1b1370d086
official/targets: uniformize, improve presentation
2019-12-03 09:07:09 +01:00
4e13b7fdab
targets: fomu: move SoCCore import definition
...
The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
626533ce9d
2019-11-25 12:46:21 +08:00
0da263fa75
platforms: fomu: add spiflash4x definition
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Fomu Hacker supports dual spi, so add a "spiflash4x" definition.
The litex spi_flash module will run this flash in dual mode, because the
`dq` array is only two signals wide.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-24 21:56:57 +08:00
45b847b466
fomu: add documentation to crg
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This documentation can be fetched using a package such as lxsocdoc.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-23 12:55:26 +08:00
2c82e02df9
fomu: pvt: swap miso and mosi
...
These pins were swapped in the definition, which made them not work so
well.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-22 18:57:26 +08:00
4231d59901
platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling)
2019-11-16 09:40:30 +01:00
2a0fbcadd2
ac701: add pcie_x1 pins
2019-11-06 09:29:55 +01:00
5bd8c4d74f
targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build)
2019-11-01 10:52:56 +01:00
1ae26dd499
targets: use type="io" instead of io_region=True
2019-10-30 16:35:32 +01:00
05a0d5fa3d
Merge pull request #21 from gsomlo/gls-sync-litex
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Gls sync litex
2019-10-30 09:47:55 +01:00
8878c0a84a
versa_ecp5, trellisboard: add trellis toolchain specific arguments
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Sync up with Litex commit #49372852d.
2019-10-29 12:32:41 -04:00
5f80633154
targets: increase integrated ROM size if EthernetSoC used
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Sync up with litex commit #201218b2c.
2019-10-29 12:32:41 -04:00
c83e10d9f3
official/platforms/versa_ecp5: add serdes refclk/sma
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Sync up with litex commit #ae9c25b74.
2019-10-29 12:32:41 -04:00
91083f99a8
ulx3s: simplify SDRAM module selection
2019-10-13 21:15:22 +02:00
6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target
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memory device selection for ulx3s
2019-10-13 20:59:16 +02:00
abf6f7b09a
memory device selection for ulx3s
2019-10-13 09:27:33 -07:00
53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target
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add sys clock freq flag, uses same method as current versa code
2019-10-13 10:32:43 +02:00
34507eb431
add sys clock freq flag, uses same method as current versa code
2019-10-13 00:44:07 -07:00
92cfd629df
partners: fomu-evt: add "dbg" connector
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This connector is for the six "debug" pins on the Raspberry Pi header.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-11 21:39:19 +08:00
09a55d20c1
partners: fomu-evt: fix spiflash4x pin mapping
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The D3 and D4 pins were swapped around, leading to interesting issues.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-11 21:38:50 +08:00
785909ac5f
targets: switch from shadow_base to io_regions
2019-10-09 11:09:59 +02:00
19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates
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Fomu cpu updates
2019-09-27 16:55:27 +08:00
c20c489d66
fomu-evt: add i2c pins
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-27 11:26:23 +08:00
48cd1208df
targets: sync with litex targets
2019-09-25 14:09:25 +02:00
0ead12bae8
targets/ulx3s: revert to cl=2
2019-09-25 13:58:45 +02:00
c8e8f254ca
targets: fomu: add USBSoC and default to heap placer
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The heap placer is important enough that we should just make it the
default.
Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:08:05 +08:00
218bd353c1
targets: fomu: use memory array for sram address
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Use the memory array to find the address for the sram bank.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:07:26 +08:00
348677598d
targets: fomu: support building with a cpu
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Allow the user to specify a CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:06:23 +08:00
e94c6c8f27
partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16)
2019-09-12 09:52:13 +02:00
91feb59f49
Merge branch 'master' of http://github.com/litex-hub/litex-boards
2019-09-11 23:02:44 +02:00
a92ce32f91
targets/netv2: add clk100 (for framebuffer)
2019-09-11 23:02:21 +02:00
ec97d01feb
platforms/netv2: add spiflashx4, hdmi in/out
2019-09-11 23:01:58 +02:00
91a1520655
add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet
2019-09-10 11:32:29 +02:00
c6bb34d78a
partner/targets/nereid: MT8KTF51264 now in LiteDRAM
2019-09-09 08:50:06 +02:00
b4eefa6c33
import: allow importing directly from litex_boards.platforms or litex_boards.targets
2019-09-03 15:30:20 +02:00
ec5540454b
partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic
2019-09-02 11:43:30 +02:00
5b605d37a2
Merge pull request #16 from rohitk-singh/master
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partner: add platforms and targets for aller, tagus and nereid boards
2019-09-02 11:31:46 +02:00
cd527f0fcb
Merge branch 'master' into master
2019-09-02 11:29:22 +02:00
d78965ffb2
partner/targets/fomu fix copyright & mode
2019-09-02 11:23:43 +02:00
46a0978d35
Merge pull request #17 from xobs/add-fomu-target
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partner: add fomu target
2019-09-02 11:18:53 +02:00
bdbd2ec1c0
partner: add fomu target
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This adds the Fomu target back in. The default BaseSoC supports
various USB methods, and will be updated as more become available.
The debug bridge may optionally be added.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:18:09 +08:00
e704014b36
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
2019-09-01 11:43:21 +02:00
346621b9fc
partner: add platforms and targets for aller, tagus and nereid boards
2019-09-01 03:02:04 -05:00
1131af05af
nexys_video: generate clk100
2019-08-27 14:05:07 +02:00
Florent Kermarrec
Sean Cross
Gabriel Somlo
Steven Osborn
Antti Lukats
Rohit Singh