3d8106f84d
stlv7325: fix Ethernet IO voltages
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The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.
Fix this in the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
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Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
4ba5793822
sitlinv_stlv7325: remove unexistent COL/CRS pins
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The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.
Remove these pins from the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
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As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
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The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform
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platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 22:11:25 +01:00
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
24cd983b8c
platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 21:52:00 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
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The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
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targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name
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platforms/nexys4*: Update part name
2022-10-27 12:11:07 +02:00
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
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targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
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Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
d4b2461b5a
platforms/nexys4*: Update part name
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Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
2022-10-21 14:15:27 -05:00
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
377cda05a3
ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity.
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Will need to be investigated more.
2022-10-20 18:21:52 +02:00
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
745ebbbfa1
Add ISX iM1283 board
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ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build
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targets/digilent_arty_z7: add flash region
2022-10-14 15:49:52 +02:00
23c6acd013
platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks.
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Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.
Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+ table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
2022-10-14 10:22:54 +02:00
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
3b339ba9a3
platforms/xilinx_kc705: Fix flash proxy name.
2022-10-13 08:48:33 +02:00
99888c52ce
xilinx_kc705/i2c: Add pullups.
2022-10-11 17:26:06 +02:00
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00
c38b8b1d8c
MNT RKX7: update platform and target for D-2 release
2022-10-03 20:09:48 +02:00
cf416d0d66
stlv7325: Adjust DDR3 pins to match reference design
2022-10-01 11:15:47 +02:00
85ba931a3d
targets/litex_acorn_baseboard: fix pn_swap
2022-09-28 21:17:16 +02:00
57eb907210
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute
2022-09-25 23:13:44 +02:00
8c3a5c0608
sipeed_tang_nano_9k: Fix HDMI IOs constraints.
2022-09-23 11:18:30 +02:00
9cd1c1cbd5
targets/digilent_arty: Switch with_buttons to False by default (To fix #426 ).
2022-09-23 10:07:17 +02:00
9dbee62eac
add option to use ecpprog for crosslink-nx eval board
2022-09-15 12:27:08 -07:00
3cef11e04d
platforms/newae_cw305: Add sma_clk_in/out, buttons, switches and expansion header connector.
2022-09-13 14:26:52 +02:00
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
25c28d2c03
fixed issue with default programmer option
2022-09-10 18:16:04 +01:00
6768be7f66
changed use example comment
2022-09-10 17:56:02 +01:00
e8504191e3
cleanup
2022-09-10 17:54:43 +01:00
6d0a4c788e
Added DFU support to Butterstick
2022-09-10 17:45:57 +01:00
756e4f73fc
sipeed_tang_primer_20k: Cleanup CRG.
2022-09-08 17:27:41 +02:00
fadc5619f1
sipeed_tang_primer_20k/ddr3: Add litescope debug.
2022-09-07 17:46:46 +02:00
6c7157f799
sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.
2022-09-07 17:07:07 +02:00
d39d87b701
sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.
2022-09-07 12:06:22 +02:00
1663ded641
sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).
2022-09-07 11:53:24 +02:00
c9b8579ea3
sipeed_tang_primer_20k: Drive hdmi hdp to 1.
2022-09-07 11:22:02 +02:00
abd20f560b
sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x).
2022-09-07 10:56:17 +02:00
1d92443604
targets/sipeed_tang_nano_9k: replace VideoHDMIPHY by VideoGowinHDMIPHY
2022-09-06 20:22:32 +02:00
4d72c75f49
platforms/sipeed_tang_primer_20k: use replace _connectors.extend by add_connector
2022-09-06 20:19:37 +02:00
0f242629ab
targets/sipeed_tang_nano_4k: replacing VideoHDMIPHY by VideoGowinHDMIPHY and adding with-video-terminal arg
2022-09-06 19:08:01 +02:00
ce5977bc1a
targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration)
2022-08-31 13:32:23 +02:00
74d4a72494
radiona/ulx3s: Rename user_button to user_btn (consistency with other boards) and fix ident.
2022-08-26 22:25:54 +02:00
693cce73bd
Merge pull request #417 from Igor542/master
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radiona_ulx3s: add buttons
2022-08-26 22:24:05 +02:00
0c14bbf0dc
sipeed_tang_primer_20k: adding dock lite support
2022-08-26 08:43:57 +02:00
9ed3b7baae
radiona_ulx3s: add buttons
2022-08-25 22:19:48 -07:00
94d079f469
sipeed_tang_nano_4k: Fix tab/space.
2022-08-24 16:07:18 +02:00
feff243f8f
Merge pull request #416 from shenki/artix-dc-scm
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Add Antmicro Artix DC-SCM board
2022-08-24 15:22:52 +02:00
6314b34dbe
targets/digilent_arty: Cosmetic cleanup.
2022-08-24 15:17:06 +02:00
6548dec149
Merge pull request #415 from lschuermann/dev/arty-button-irq
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digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
2022-08-24 15:15:20 +02:00
6ba6a7e8fa
Merge pull request #414 from lambdaconcept/master
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lambdaconcept_ecpix5: fix HDMI pin
2022-08-24 15:14:11 +02:00
f48ed3d9e7
Add Antmicro Artix DC-SCM board
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Based on commits by:
- Jedrzej Boczar <jboczar@antmicro.com>
- Karol Gugala <kgugala@antmicro.com>
Tested serial and networking on a DC-SCM with mor1k and vexriscv.
2022-08-24 13:03:36 +10:00
94ad22aceb
digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
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Signed-off-by: Leon Schuermann <leon@is.currently.online>
2022-08-17 15:55:39 +02:00
c3e99a8419
lambdaconcept_ecpix5: fix HDMI pin
2022-08-11 18:45:10 +02:00
7487440725
Added Tang Nano 4k Support for GoWin Educational IDE v1.9.8.03
2022-08-05 13:28:22 -03:00
bf458e388e
digilent_arty: Add buttons support.
2022-08-05 15:25:42 +02:00
f143fae2d0
digilent_arty: Add XADC/DNA and do minor cleanups.
2022-08-05 13:00:07 +02:00
6872f7ade6
sipeed_tang_primer_20k: Add LCD pins (untested).
2022-08-05 09:42:38 +02:00
c79d01064e
sipeed_tang_primer_20k: Switch Serial to Dock IOs.
2022-08-05 09:07:20 +02:00
f2cb211432
sipeed_tang_primer_20k: Add buttons and prepare RGB Led.
...
Synthesis issue with WS2812/GowinEDA for now.
2022-08-04 16:32:50 +02:00
09b0c975f3
sipeed_tang_primer_20k: Add Ethernet/Etherbone (compiles but not yet working).
2022-07-26 12:53:42 +02:00
abe08a96aa
sipeed_tang_primer_20k: Add Video (Colorbars), compiles but does not seems to be working.
2022-07-26 12:25:10 +02:00
12b8063941
sipeed_tang_primer_20k: Add LedChaser through 204 pin SODIMM connector/Dock.
2022-07-26 11:44:03 +02:00
d49e43801e
sipeed_tang_primer_20k: Add 204 Pins SODIMM Connector.
...
Will allow defining Dock peripherals.
2022-07-26 11:30:39 +02:00
99c1e52664
targets/sipeed_tang_primier_20k: Add SPI Flash support (X1).
2022-07-26 10:35:44 +02:00
6677c1d0bd
sipeed_tang_primer_20k: Enable SDCard (SPI and SD modes).
2022-07-26 10:27:19 +02:00
cf030402d4
machdyne_krote: Fix build.
2022-07-19 12:17:14 +02:00
67ffe095cc
Merge branch 'master' of https://github.com/machdyne/litex-boards
2022-07-15 17:13:22 +02:00
22dcadcfa1
rename ld board prefix to machdyne
2022-07-15 17:13:00 +02:00
9deef65445
Merge branch 'litex-hub:master' into master
2022-07-14 16:02:00 +02:00
52ff93a194
Merge pull request #409 from antmicro/rrozak/remove-dm-pins-from-datacenter
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Remove DM signals assignment from DDR4 Datacenter platform
2022-07-11 19:34:19 +02:00
8e577662bd
Merge pull request #408 from trabucayre/lattice_nexus_ecp5_toolchain
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targets: ecp5 & nexus: add toolchain argument
2022-07-11 19:33:54 +02:00
2357212161
Remove DM signals assignment from DDR4 Datacenter platform
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Data Masks (DM) are unsupported on x4 devices and wrong pins were assigned.
Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-07-11 12:29:02 +02:00
3ecec8cd16
Merge branch 'litex-hub:master' into master
2022-07-08 16:59:55 +02:00
Icenowy Zheng
Florent Kermarrec
Gwenhael Goavec-Merou
Chema
Shawn Anastasio
Franck Jullien
Lukas F. Hartmann
Vadzim Dambrouski
slagernate
Adam Zeloof
Igor Safonov
Joel Stanley
Leon Schuermann
Pierre-Olivier Vauboin
Chandler Klüser
inc
Machdyne
Ryszard Różak