litex-boards/litex_boards/targets
enjoy-digital 2e120bf8a4
Merge pull request #570 from disdi/master
Add support for CTUCAN for Arty & Genesys2 board
2024-07-05 09:21:09 +02:00
..
__init__.py Move import Compat directly to litex_boards.__init__.py and simplify. 2021-03-25 16:47:47 +01:00
adi_adrv2crr_fmc.py di_adrv2crr_fmc: Bump PCIe to 8 lanes 2024-02-05 11:43:02 +01:00
adi_plutosdr.py
alchitry_au.py
alchitry_cu.py
alchitry_mojo.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alientek_davincipro.py
aliexpress_xc7k70t.py aliexpress_xc7k70t: Review/Cleanup. 2023-11-09 08:26:06 +01:00
aliexpress_xc7k420t.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alinx_ax7010.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
alinx_axau15.py
alinx_axu2cga.py targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU 2024-06-19 07:54:50 +02:00
analog_pocket.py
antmicro_artix_dc_scm.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
antmicro_datacenter_ddr4_test_board.py target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
antmicro_lpddr4_test_board.py
antmicro_sdi_mipi_video_converter.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
arduino_mkrvidor4000.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
avnet_aesku40.py
berkeleylab_marble.py
camlink_4k.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
colognechip_gatemate_evb.py
colorlight_5a_75x.py
colorlight_i5.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
colorlight_i9plus.py
decklink_intensity_pro_4k.py
decklink_mini_4k.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
decklink_quad_hdmi_recorder.py
digilent_arty.py Add support for CTUCAN for Arty board 2024-03-05 11:53:54 +01:00
digilent_arty_s7.py
digilent_arty_z7.py
digilent_atlys.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_basys3.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_cmod_a7.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
digilent_genesys2.py Add support for CTUCAN for Genesys2 board 2024-03-13 06:51:48 +01:00
digilent_nexys4.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
digilent_nexys4ddr.py
digilent_nexys_video.py targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use. 2023-11-07 13:22:30 +01:00
digilent_pynq_z1.py
digilent_zedboard.py
ebaz4205.py
efinix_t8f81_dev_kit.py
efinix_titanium_ti60_f225_dev_kit.py target/efinix_ti60_f225: Add L2 Cache (16KB for now) to improve perfs/Coremark. 2024-04-23 11:45:07 +02:00
efinix_trion_t20_bga256_dev_kit.py targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset 2024-06-24 09:14:55 +02:00
efinix_trion_t20_mipi_dev_kit.py
efinix_trion_t120_bga576_dev_kit.py targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs. 2023-08-30 09:59:23 +02:00
efinix_xyloni_dev_kit.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
ego1.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
enclustra_mercury_kx2.py copyright notices on enclustra 2023-04-11 10:29:52 +07:00
enclustra_mercury_xu5.py
fairwaves_xtrx.py
fpc_iii.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
fpgawars_alhambra2.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
gadgetfactory_papilio_pro.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
gsd_butterstick.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
gsd_orangecrab.py
hackaday_hadbadge.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
hseda_xc7a35t.py Add HSEDA XC7A35T board support 2024-05-21 21:00:27 +08:00
ice_v_wireless.py
icebreaker.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
icebreaker_bitsy.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
isx_im1283.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
jungle_electronics_fireant.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
kosagi_fomu.py
kosagi_netv2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
krtkl_snickerdoodle.py
lambdaconcept_ecpix5.py targets/lambdaconcept_ecpix5.py: allows configuring eth_ip/remote_ip/dynamic 2024-06-14 15:58:25 +02:00
lattice_certuspro_nx_evn.py targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL 2024-07-03 12:36:28 +02:00
lattice_certuspro_nx_vvml.py targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL 2024-07-03 12:36:28 +02:00
lattice_crosslink_nx_evn.py
lattice_crosslink_nx_vip.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
lattice_ecp5_evn.py
lattice_ecp5_vip.py
lattice_ice40up5k_evn.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
lattice_versa_ecp5.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
limesdr_mini_v2.py targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart 2024-04-11 15:12:17 +02:00
linsn_rv901t.py
litex_acorn_baseboard.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
litex_acorn_baseboard_mini.py
logicbone.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
machdyne_konfekt.py
machdyne_kopflos.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_krote.py
machdyne_lakritz.py
machdyne_minze.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_ml1.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_mozart_ml2.py
machdyne_mozart_mx1.py
machdyne_noir.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
machdyne_schoko.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
machdyne_vanille.py
machdyne_vivaldi_ml1.py machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1 2024-06-22 11:26:43 +02:00
micronova_mercury2.py
mist.py
mnt_rkx7.py
muselab_icesugar.py
muselab_icesugar_pro.py
myminieye_runber.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
newae_cw305.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
numato_aller.py
numato_mimas_a7.py
numato_nereid.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
numato_tagus.py
ocp_tap_timecard.py
olimex_gatemate_a1_evb.py Olimex GateMate A1 EVB: new Board 2024-03-02 12:23:27 +01:00
opalkelly_xem8320.py
pano_logic_g2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_5cefa2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_5cefa5.py
qmtech_10cl006.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
qmtech_artix7_fbg484.py qmtech_artix7_fgg676: fix wrong memory chip type 2024-03-29 08:41:19 +07:00
qmtech_artix7_fgg676.py qmtech_artix7_fgg676: fix wrong memory chip type 2024-03-29 08:41:19 +07:00
qmtech_ep4ce15_starter_kit.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
qmtech_ep4cex5.py
qmtech_ep4cgx150.py
qmtech_kintex7_devboard.py target/qmtech_kintex7_devboard: +X. 2024-02-26 15:41:09 +01:00
qmtech_wukong.py qmtech_wukong: Switch to direct instance of LiteEthPHYGMII since hybrid MII/GMII does not seems to work correctly. 2024-03-28 16:02:55 +01:00
qmtech_xc7a35t.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
qmtech_xc7k325t.py
quicklogic_quickfeather.py
qwertyembedded_beaglewire.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
radiona_ulx3s.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
radiona_ulx4m_ld_v2.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
rcs_arctic_tern_bmc_card.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
redpitaya.py
rz_easyfpga.py
saanlima_pipistrello.py
scarabhardware_minispartan6.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
seeedstudio_spartan_edge_accelerator.py
siglent_sds1104xe.py
simple.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
sipeed_tang_mega_138k_pro.py Finish tang_mega_138k renaming to tang_mega_138k_pro. 2024-03-26 21:58:02 +01:00
sipeed_tang_nano.py target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
sipeed_tang_nano_4k.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
sipeed_tang_nano_9k.py
sipeed_tang_nano_20k.py fix help text 2023-10-12 11:21:20 -04:00
sipeed_tang_primer.py
sipeed_tang_primer_20k.py sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. 2023-08-29 16:50:17 +02:00
sipeed_tang_primer_25k.py sipeed_tang_primer_25k: new board 2023-10-17 07:45:40 +02:00
sitlinv_a_e115fb.py
sitlinv_stlv7325_v1.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
sitlinv_stlv7325_v2.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
sitlinv_xc7k420t.py
sqrl_acorn.py targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman). 2023-09-27 11:06:50 +02:00
sqrl_fk33.py
sqrl_xcu1525.py
terasic_de0nano.py
terasic_de1soc.py
terasic_de2_115.py terasic_de2_115: Cosmetic cleanup. 2023-11-06 19:21:53 +01:00
terasic_de10lite.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_de10nano.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
terasic_deca.py target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
terasic_sockit.py
tinyfpga_bx.py targets: Switch to LiteX byte size definitions. 2024-06-13 10:04:19 +02:00
trellisboard.py
trenz_c10lprefkit.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_cyc1000.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_max1000.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_te0725.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
trenz_tec0117.py
tul_pynq_z2.py
xilinx_ac701.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_alveo_u200.py Fix Memory initialization of Alveo U200 failed #1606 2023-04-17 18:59:50 +07:00
xilinx_alveo_u250.py Fix Memory test failure of Alveo U250 2023-04-24 17:35:58 +09:00
xilinx_alveo_u280.py target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
xilinx_kc705.py xilinx_kc705: Minor Cleanup/Update. 2024-03-27 08:48:05 +01:00
xilinx_kcu105.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_kv260.py
xilinx_vc707.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_vcu118.py targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
xilinx_vcu128.py
xilinx_zc706.py platforms,targets/xilinx_zc706: added choice between vivado(default) and openFPGALoader, re-enable DDR 2024-04-08 20:38:09 +02:00
xilinx_zcu102.py targets/xilinx_zcu102: Add litedram to the target. 2023-10-14 00:00:26 +09:00
xilinx_zcu104.py
xilinx_zcu106.py
xilinx_zcu216.py targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU 2024-06-19 07:54:50 +02:00
xilinx_zybo_z7.py
ztex213.py