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9752 Commits

Author SHA1 Message Date
Fin Maaß cd457c9809 soc: add l2 cache to spi_ram 
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-08-01 15:51:45 +02:00
Matthias Breithaupt e29dc39377 openocd/jtagspi: Allow users to specify additional init commands 
This change makes it possible to e.g. use flahs chips that would not be correctly detected by OpenOCD.
All that has to be done is to add `init_commands=["jtagspi set 0 \"name\" {size} {pagesize} {read_cmd} 0 {pprg_cmd} {mass_erase_cmd} {sector_size} {sector_erase_cmd}"]`.

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-08-01 15:51:45 +02:00
Matthias Breithaupt 41b346d141 bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses) 
Instead of reading each individual byte, causing multiple 4-byte requests to each address, this
change results in a single read for each address.

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-08-01 15:51:45 +02:00
Matthias Breithaupt 03a0a6fd9b soc: add add_spi_ram function 
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-08-01 15:51:45 +02:00
Florent Kermarrec f855417afc README.md: Be more positive and shorter in moral precisions :). 2024-07-31 14:55:10 +02:00
enjoy-digital 74127d51c5
Merge pull request #2024 from trabucayre/altera_agilex5_sdrtristate_special 
build/altera/common.py: implement SDRTristate for Agilex5 family
 2024-07-30 19:22:25 +02:00
Gwenhael Goavec-Merou 1f6673c6eb build/altera/common.py: implement SDRTristate for Agilex5 family 2024-07-30 16:36:05 +02:00
enjoy-digital 3041150773
Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special 
build/altera/common,platform: added ddrinput/ddrout primitives
 2024-07-26 18:26:19 +02:00
Florent Kermarrec ba8830e6cd global: Remove @trabucayre's tracers :) 2024-07-26 12:57:01 +02:00
Florent Kermarrec 5c5bc82f22 interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid. 
Needs to be filtered on param_fifo.sink.ready and not payload_fifo.sink.ready.
 2024-07-26 11:52:17 +02:00
Gwenhael Goavec-Merou dc04949d78 build/altera/common,platform: added ddrinput/ddrout primitives 2024-07-25 14:11:06 +02:00
Florent Kermarrec c51d22074f soc/integration/soc/add_uart: Allow directly passing uart_pads. 
Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
 2024-07-22 16:23:22 +02:00
Gwenhael Goavec-Merou b8cb6da2b9 soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output 2024-07-22 15:11:40 +02:00
Florent Kermarrec ecd0f0e548 cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K. 2024-07-22 14:24:34 +02:00
enjoy-digital 4662b95f16
Merge pull request #2012 from machdyne/master 
soc/cores/video: Add additional color formats
 2024-07-21 09:34:00 +02:00
enjoy-digital 4301293b21
Merge pull request #2018 from motec-research/add_i2c_master 
Add i2c master
 2024-07-21 09:32:48 +02:00
Andrew Dennison 67e6614eb2 test_i2c: whitespace cleanups 2024-07-20 15:45:44 +10:00
Radek Pesina 643f3f9a93 test_i2c: add more commands 2024-07-20 15:45:44 +10:00
Andrew Dennison f99658200e soc/cores/i2c: rewrite state machine 
* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
 2024-07-20 15:45:44 +10:00
Andrew Dennison 13811aeacb test_i2c: update to use improved _MockTristate 
* test now checks the actual i2c bus state, not the I2CMaster output
* refactor to eliminate some copy/paste
* tests now work again with this change: 'only change SDA when SCL is stable'
 2024-07-20 15:45:44 +10:00
Andrew Dennison b779933a5f test_i2c: improve and document _MockTristate* 
Added i_mock for simulated external device:
    * when _oe = 0 _i = _i_mock
    * when _oe = 1 _i = _o
 2024-07-20 15:45:44 +10:00
Andrew Dennison dce152b348 soc/cores/i2c: change SDA 1 or 2 cycles earlier 
* update 'only change SDA when SCL is stable' to max 1 sys_clk delay
 2024-07-20 15:45:44 +10:00
Andrew Dennison e36946b251 soc/cores/i2c: convert to LiteXModule and name some components 2024-07-20 15:45:44 +10:00
Andrew Dennison c867d5647b soc/cores/i2c: only change SDA when SCL is stable 
Avoid changing SDA immediately in states WRITE0 and READ0 to guarantee SDA hold is > 0
 2024-07-20 15:45:44 +10:00
Andrew Dennison aef6cb3103 soc/cores/i2c: remove unnecessary code 2024-07-20 15:45:44 +10:00
Andrew Dennison 64ccd6df1c test_i2c: allow unit test to run directly 2024-07-20 15:45:44 +10:00
Richard Tucker 5504cc626f soc/cores/i2c: change ISR to rising edge of idle 2024-07-20 15:45:44 +10:00
Richard Tucker b8b6ecef7c soc/cores/i2c: fix CSR generation 2024-07-20 15:45:44 +10:00
Andrew Dennison 90128756f9 test_i2c: test reading config 2024-07-20 15:45:44 +10:00
Andrew Dennison ad37e17743 soc/cores/i2c: add interrupt 2024-07-20 15:45:44 +10:00
Andrew Dennison 4ddab34714 test_i2c: generate i2c.vcd 2024-07-20 15:45:44 +10:00
Andrew Dennison a079da922a soc/cores: adapt misoc i2c to litex 
Also add misoc license information.
 2024-07-20 15:45:44 +10:00
Andrew Dennison 9dc3eefb7d soc/cores/i2c: import from misoc 
* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
 2024-07-20 15:45:44 +10:00
Florent Kermarrec a014c4f07c tools/litex_sim: Cleanup imports. 2024-07-18 12:16:23 +02:00
Dolu1990 8a08d5ca19
Merge pull request #2017 from Dolu1990/vexiiriscv 
Fix VexiiRiscv
 2024-07-18 11:37:03 +02:00
Dolu1990 cbe7413fee Fix VexiiRiscv 2024-07-18 11:32:07 +02:00
enjoy-digital 1b9bdbdce4
Merge pull request #2016 from Dolu1990/vexiiriscv 
Update VexiiRiscv
 2024-07-18 11:27:20 +02:00
Dolu1990 f687425cb1 Update VexiiRiscv 2024-07-18 11:26:13 +02:00
Dolu1990 473784581d
Merge pull request #2011 from Dolu1990/vexiiriscv 
cpu: Vexii/Nax fmax / area improvements
 2024-07-12 17:29:45 +02:00
Dolu1990 9fa1b4c123 Update Nax/Vexii 2024-07-12 16:17:30 +02:00
inc aef5a2094e soc/cores/video: Add additional color formats 2024-07-10 15:21:51 +02:00
Dolu1990 22ff3ac42d Merge branch 'master' into vexiiriscv 
# Conflicts:
#	litex/soc/cores/cpu/vexiiriscv/core.py
 2024-07-10 09:37:43 +02:00
Dolu1990 1267ba8ae6 Update Nax/Vexii 2024-07-10 09:35:34 +02:00
Florent Kermarrec e4e9bd2125 interconnect/axi/axi_lite: Add bursting property even if always False. 2024-07-09 17:02:54 +02:00
Dolu1990 372ab25273 Merge branch 'nax64_irq' into vexiiriscv 2024-07-09 15:18:25 +02:00
Florent Kermarrec 549d23e4f7 build/efinix: Add default parameter values and fix other typos. 2024-07-09 10:04:03 +02:00
Florent Kermarrec e6171e79db build/efinix: Fix typos (thanks @AndrewD). 2024-07-09 10:00:21 +02:00
enjoy-digital 7de4f01aa8
Merge pull request #2009 from trabucayre/efinix_args_opts 
build/efinix: added argument to change synthesis options configurations
 2024-07-08 17:01:28 +02:00
Gwenhael Goavec-Merou ec1528fb69 build/efinix: added argument to change synthesis options configurations 2024-07-08 15:59:30 +02:00
Florent Kermarrec 0db650ac6a soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic). 2024-07-05 13:56:14 +02:00