Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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e4de5a0c9d
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make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
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2015-02-27 10:23:17 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
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Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
Robert Jordens
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2b12679ef6
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add pipistrello target
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2015-02-26 21:35:42 -07:00 |
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Robert Jordens
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c9ed38dec8
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gensoc: missing self.
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2015-02-26 21:32:11 -07:00 |
Sebastien Bourdeauducq
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a3909bb5e2
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-02-26 21:28:12 -07:00 |
Yann Sionneau
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8364fe6674
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target/kc705: allow access to pll_sys signal before BUFG
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2015-02-26 15:56:10 -07:00 |
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Florent Kermarrec
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09fbbca53e
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gensoc: cpus now directly add their verilog sources
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2015-02-26 20:49:21 +01:00 |
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Florent Kermarrec
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5e8a0c496d
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gensoc: add mem_map and mem_decoder to avoid duplications
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2015-02-26 20:12:27 +01:00 |
|
Florent Kermarrec
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5ac5ffe359
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gensoc: get platform_id from platform
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2015-02-26 19:07:19 +01:00 |
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Florent Kermarrec
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554731ae44
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targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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2015-02-26 13:08:15 +01:00 |
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Florent Kermarrec
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02b3f51382
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liteeth: fix example_designs generation
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2015-02-26 10:23:38 +01:00 |
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Florent Kermarrec
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00862a383c
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liteeth: fix import (from liteeth --> from misoclib.liteeth)
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2015-02-26 09:48:37 +01:00 |
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Florent Kermarrec
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60effe1d95
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move files to liteeeth and create example_designs directory
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2015-02-26 09:35:14 +01:00 |
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Sebastien Bourdeauducq
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0267868cbe
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remove litex submodule
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2015-02-25 10:40:44 -07:00 |
|
Sebastien Bourdeauducq
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658cb0e405
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merge liteeth
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2015-02-25 10:35:39 -07:00 |
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Sebastien Bourdeauducq
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8015d12692
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move files for misoc integration
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2015-02-25 10:34:11 -07:00 |
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Florent Kermarrec
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eef679b6d4
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phy/sim: generate sop/eop
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2015-02-25 17:47:44 +01:00 |
|
Florent Kermarrec
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a559fc77c8
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remove upload optimization (we will use wishbone later for performance)
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2015-02-24 18:01:04 +01:00 |
|
Florent Kermarrec
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6b7026f521
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add sim phy
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2015-02-24 01:42:56 +01:00 |
|
Florent Kermarrec
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b6ebcece95
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add read grouping to etherbone, we now have interesting upload speeds... :)
|
2015-02-23 18:58:31 +01:00 |
|
Florent Kermarrec
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ac5b7c073a
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test: add make.py to replace static config.py file
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2015-02-23 18:55:19 +01:00 |
|
Florent Kermarrec
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71f3a5bf13
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prepare reads grouping to speed up upload
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2015-02-23 18:11:08 +01:00 |
|
Florent Kermarrec
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e309ba55ea
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use new Migen sel signal to change the way we upload data (will enable fifo bursts)
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2015-02-23 12:34:04 +01:00 |
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Florent Kermarrec
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d3486dba91
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rle: increase dw automatically when needed
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2015-02-23 09:41:18 +01:00 |
|
Florent Kermarrec
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2a2c3af380
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host/dump: optimize get_bits / decode_rle since we can now have large dumps
|
2015-02-23 02:14:20 +01:00 |
|
Florent Kermarrec
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861c54760e
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host/driver/reg: use burst mode to speed up upload of data (useful with Etherbone)
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2015-02-23 00:49:59 +01:00 |
|
Florent Kermarrec
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282c9b9426
|
test: add make.py to replace static config.py file
|
2015-02-23 00:21:12 +01:00 |
|
Florent Kermarrec
|
b1dee774cd
|
tty working
|
2015-02-22 15:23:55 +01:00 |
|
Florent Kermarrec
|
2fa28c1b5d
|
mac: add padding
|
2015-02-22 13:56:06 +01:00 |
|
Florent Kermarrec
|
a802a5c535
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remove MiSoC dependency
|
2015-02-21 23:50:25 +01:00 |
|
Florent Kermarrec
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a2370388fb
|
doc: remove IP
|
2015-02-21 23:34:30 +01:00 |
|
Florent Kermarrec
|
15240912c9
|
doc: remove IP
|
2015-02-21 23:34:08 +01:00 |
|
Florent Kermarrec
|
ea7962da12
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doc: remove IP
|
2015-02-21 23:33:49 +01:00 |
|
Florent Kermarrec
|
acdf511bd1
|
doc: remove IP
|
2015-02-21 23:33:21 +01:00 |
|
Florent Kermarrec
|
7837580020
|
add ft2232h software code (will need rework)
|
2015-02-21 23:19:10 +01:00 |
|
Florent Kermarrec
|
b59c777cab
|
add ft2232h hdl code (will need rework)
|
2015-02-21 23:13:43 +01:00 |
|
Florent Kermarrec
|
1b0bc5ca44
|
init repo structure
|
2015-02-21 23:06:36 +01:00 |
|
Florent Kermarrec
|
4bdb1ffda2
|
add README skeleton
|
2015-02-21 22:58:42 +01:00 |
|
Florent Kermarrec
|
65294a5577
|
add tty over udp (will need mac to insert padding)
|
2015-02-21 21:26:52 +01:00 |
|
Florent Kermarrec
|
0a9043b6c1
|
remove MiSoC dependency
|
2015-02-21 19:34:14 +01:00 |
|
Florent Kermarrec
|
52f5955dca
|
remove MiSoC dependency
|
2015-02-21 19:29:26 +01:00 |
|
Florent Kermarrec
|
741ecca5b4
|
la: fix intput_buffer clocking when clk_domain is not "sys"
|
2015-02-19 11:41:54 +01:00 |
|
Florent Kermarrec
|
37e463da9a
|
fix rle when used with subsampler
|
2015-02-19 11:34:20 +01:00 |
|
Florent Kermarrec
|
e495e2f537
|
driver/la: add samplerate computation (required by sigrok export)
|
2015-02-19 11:16:32 +01:00 |
|
Florent Kermarrec
|
8e0553670a
|
remove limitation on debug tuple definition
|
2015-02-19 10:52:57 +01:00 |
|
Florent Kermarrec
|
5f19955825
|
rle: expose length parameter to user, add assertion on dw to encode counter and automatically increase dw in rle mode
|
2015-02-19 10:42:13 +01:00 |
|
Florent Kermarrec
|
5fb6beb473
|
enable RLE only in POST_HIT_RECORDING state (to ensure programmed offset is respected)
|
2015-02-19 10:26:34 +01:00 |
|
Florent Kermarrec
|
788652c6f8
|
simplify RLE
|
2015-02-19 01:43:04 +01:00 |