09003a55e1
fhdl/specials/Tristate: handle i=None
2015-09-26 21:49:12 +08:00
e136352e8f
fhdl/structure: relax type requirements for Array elements
2015-09-26 21:47:33 +08:00
808cf06add
fhdl: replace flen with len
2015-09-26 18:45:10 +08:00
fa1e8cd822
wrap expressions in Specials
2015-09-26 16:45:13 +08:00
8f42b6f352
fhdl: introduce wrap function
2015-09-26 15:36:28 +08:00
67903494bf
fhdl: export DUID
2015-09-26 13:46:57 +08:00
af88a7a3f9
setup: simpler version check, beta status
2015-09-24 16:08:39 +08:00
33f344b92a
fsm: NextState and NextValue should derive from _Statement
2015-09-23 22:38:10 +08:00
8935ca2c9f
setup: remove unneeded import
2015-09-23 09:52:24 +08:00
8421549935
README.md->rst
2015-09-23 00:55:37 +08:00
8534562185
sim: fix slice assign
2015-09-22 20:33:44 +08:00
88f9d72e74
conda: use new branch (revert this after merge)
2015-09-22 17:27:44 +08:00
6005548df6
setup.py: cleanup
2015-09-22 17:27:27 +08:00
31ffa8c18f
fsm: support complex targets in NextValue. Closes #27 .
2015-09-22 16:55:24 +08:00
1857ec6c32
fhdl/namer: support ClockSignal and ResetSignal. Closes #24
2015-09-22 14:30:16 +08:00
2c1553fea2
sim: insert resets, support ClockSignal and ResetSignal
2015-09-21 22:13:36 +08:00
99af825a5a
sim: drive clock signals
2015-09-21 21:53:41 +08:00
a67b4baa0c
sim: VCD output support
2015-09-21 21:20:31 +08:00
34ce6b077f
verilog: remove unneeded import
2015-09-21 21:19:58 +08:00
b8647a161d
doc: minor edits
2015-09-21 21:19:39 +08:00
2ac748aef2
doc: remove spurious file
2015-09-20 16:13:08 +08:00
74b0cfc83b
doc: remove outdated or moved parts, cleanup
2015-09-20 16:10:40 +08:00
1767eef9cb
fhdl/visit: support Constant
2015-09-20 16:10:17 +08:00
87a8531952
travis: VPI is not there for now
2015-09-20 15:12:04 +08:00
7f767095ec
sim: support generators yielding statements
2015-09-20 15:04:15 +08:00
320dffb4ac
sim: memory access from generators
2015-09-20 14:52:26 +08:00
59802bec76
fhdl/structure: add missing init
2015-09-20 14:46:30 +08:00
8bbfaa01fc
sim: memory support
2015-09-19 23:21:46 +08:00
1861ae9d01
fhdl/specials: MemoryPort.clock should always be a ClockSignal
2015-09-19 23:21:24 +08:00
262fd50677
fhdl/simplify: add MemoryToArray
2015-09-19 23:20:57 +08:00
944a0b0480
test/fifo: convert to new API
2015-09-19 23:20:30 +08:00
dcf4f7fef3
genlib/fifo: add missing import
2015-09-19 23:20:19 +08:00
9420aabc0d
sim: support arrays, and cat+slice in assignment target
2015-09-19 14:56:26 +08:00
563231fdfb
migen/genlib/cdc: fix BusSynchronizer
...
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.
This fix add a timeout to detect such situation and create another token.
2015-09-19 12:21:54 +08:00
bfcc8f9661
sim: remove unneeded import
2015-09-19 12:18:20 +08:00
84f98b4632
genlib/CRG: fix variable name conflict
2015-09-19 11:18:44 +08:00
0a55ef5bc3
test: add divider
2015-09-18 11:07:14 +08:00
ec1d4edf84
sim: support Case
2015-09-17 17:25:06 +08:00
9d3fd50950
sim: variables are deprecated
2015-09-17 17:24:57 +08:00
2688d66ea1
sim: fix comb evaluation
2015-09-17 17:24:20 +08:00
049a8f082a
test/size: do not test removed functions
2015-09-17 17:23:19 +08:00
4a3a1bc5b0
test/coding: use new API
2015-09-17 17:22:59 +08:00
12cd390c0b
genlib/misc: add missing import
2015-09-17 17:22:44 +08:00
776579f0d7
fhdl/structure: all case statements should be lists
2015-09-17 17:22:24 +08:00
bcf62997f6
fhdl/bitcontainer: remove fiter
2015-09-17 17:22:03 +08:00
c2109f8f81
minor bugfixes
2015-09-17 15:20:27 +08:00
6e08df75ee
sim: support eval of slice, cat and mux
2015-09-17 14:39:36 +08:00
9dd3200ba2
fhdl/structure: fix namespace pollution
2015-09-17 14:39:17 +08:00
6569c516a1
test: bit reverse
2015-09-17 14:38:55 +08:00
0a92e346d3
fhdl/bitcontainer: remove fslice and freversed
2015-09-17 14:38:33 +08:00
Sebastien Bourdeauducq
Florent Kermarrec