Sebastien Bourdeauducq
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973c00938d
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Reorganize examples folder
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2012-06-12 17:49:50 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
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PureSimulable
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2012-06-12 17:08:56 +02:00 |
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Sebastien Bourdeauducq
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a591510189
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ASMI simulation models
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2012-06-12 16:57:00 +02:00 |
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Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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f061b25a24
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bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
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Sebastien Bourdeauducq
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5964df62db
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examples/dataflow: only import nx when needed
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2012-06-08 22:54:04 +02:00 |
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Sebastien Bourdeauducq
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009f26bb9d
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flow/network: refactor graph
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2012-06-08 22:49:49 +02:00 |
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Sebastien Bourdeauducq
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de408b2cba
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flow/ala: fix typo
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2012-06-08 22:48:47 +02:00 |
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Sebastien Bourdeauducq
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f86170e349
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actorlib: WB writer simulation OK
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2012-06-08 21:31:57 +02:00 |
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Sebastien Bourdeauducq
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356051e8a8
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actorlib: WB reader simulation OK
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2012-06-08 21:31:05 +02:00 |
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Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
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Sebastien Bourdeauducq
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152a7e282e
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actorlib/sim: use set instead of list to represent active transactions
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2012-06-08 17:56:52 +02:00 |
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Sebastien Bourdeauducq
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910c7806cf
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actorlib: generator-based generic simulation actor
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2012-06-08 17:54:03 +02:00 |
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Sebastien Bourdeauducq
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b145f9e5e2
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sim: multiread/multiwrite
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2012-06-08 17:52:32 +02:00 |
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Sebastien Bourdeauducq
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f38ef626de
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corelogic/record: better repr
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2012-06-08 17:49:31 +02:00 |
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Sebastien Bourdeauducq
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d280723618
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examples/fir: print Verilog source
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2012-06-08 14:00:49 +02:00 |
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Sebastien Bourdeauducq
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b00e8fa826
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examples/fir: plot input and output signals
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2012-06-07 23:20:59 +02:00 |
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Sebastien Bourdeauducq
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1c0f636c8d
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flow: generic parameter passing to Actor from sequential/pipelined
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2012-06-07 18:24:33 +02:00 |
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Sebastien Bourdeauducq
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a1fc86af8f
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flow: fix actor repr
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2012-06-07 15:48:35 +02:00 |
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Sebastien Bourdeauducq
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680a34465d
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flow: refactor scheduling models
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2012-06-07 14:44:43 +02:00 |
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Sebastien Bourdeauducq
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493b181af1
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bank/description: pad unaligned multi-word registers at the top
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2012-05-21 22:55:23 +02:00 |
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Sebastien Bourdeauducq
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9449bbea0a
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Add LICENSE file
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2012-05-21 19:56:23 +02:00 |
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Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
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Sebastien Bourdeauducq
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0bea1e2589
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asmi: dat_wm high to disable data write
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2012-05-15 14:41:54 +02:00 |
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Sebastien Bourdeauducq
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f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
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398ece8fe2
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fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
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2012-04-30 16:38:40 -05:00 |
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Sebastien Bourdeauducq
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0b62e573ae
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sim: pass extra keyword arguments to Verilog converter
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2012-04-30 16:38:17 -05:00 |
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Sebastien Bourdeauducq
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6a52e44d09
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fhdl: support len() on signals
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2012-04-08 18:06:22 +02:00 |
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Sebastien Bourdeauducq
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b9c533be51
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bank/csrgen: allow specifying existing CSR interface
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2012-04-06 14:59:09 +02:00 |
Brandon Hamilton
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49b58a03a0
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Optionally accept iverilog simulator options
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2012-04-03 12:58:19 +02:00 |
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Sebastien Bourdeauducq
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2a4e49e381
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fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
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Sebastien Bourdeauducq
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1b60c7ff40
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vpi: delete merged Icarus Verilog patch
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2012-04-02 19:11:32 +02:00 |
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Sebastien Bourdeauducq
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623e8e436a
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fhdl/verilog: do not attempt to initialize instance and mem output signals
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2012-04-02 12:59:42 +02:00 |
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Sebastien Bourdeauducq
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6e3b25ebb6
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
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Sebastien Bourdeauducq
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d3c6b8d16f
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sim/proxy: support lists
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2012-04-01 17:19:53 +02:00 |
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Sebastien Bourdeauducq
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f3ae22f488
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fhdl/verilog: initialize internal read-only signals with their reset values
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2012-04-01 16:39:11 +02:00 |
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Sebastien Bourdeauducq
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0dfc215fe8
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corelogic/roundrobin: handle correctly special case with 1 request source
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2012-03-31 18:01:40 +02:00 |
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Sebastien Bourdeauducq
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94b02aa8ed
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bus/asmicon: initiator
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2012-03-30 22:16:31 +02:00 |
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Sebastien Bourdeauducq
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bb864c65dc
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sim: proxy
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2012-03-30 16:40:26 +02:00 |
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Sebastien Bourdeauducq
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081b658e2d
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Update copyright notices
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2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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d47b564fad
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corelogic/fsm: typo
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2012-03-18 22:12:46 +01:00 |
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Sebastien Bourdeauducq
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5f28103769
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corelogic/fsm: delayed enters
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2012-03-18 00:09:40 +01:00 |
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Sebastien Bourdeauducq
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a4294762d0
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corelogic/roundrobin: CE switching
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2012-03-16 16:54:47 +01:00 |
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Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
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Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
Alain Péteut
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97fece249d
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setup.py: simplify
Signed-off-by: Alain Péteut <alain.peteut@yahoo.com>
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2012-03-11 00:52:13 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
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doc: more examples and comments
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2012-03-10 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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1f4c58ee26
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doc: cosmetic changes (thanks sh4rm4 for reporting typos)
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2012-03-10 17:59:42 +01:00 |