Sebastien Bourdeauducq
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0f9df2d732
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genlib: add Gray counter
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2013-04-24 19:13:36 +02:00 |
Florent Kermarrec
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f599fe4ade
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Support for resetless clock domains
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2013-04-23 11:54:05 +02:00 |
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Sebastien Bourdeauducq
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72ef4b9683
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ioo+pytholite: use new Module API
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2013-04-10 23:42:46 +02:00 |
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Sebastien Bourdeauducq
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746acdacd1
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ioo: move to genlib
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2013-04-10 22:28:53 +02:00 |
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Sebastien Bourdeauducq
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692794a21f
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flow: use Module and new Record APIs
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2013-04-10 19:12:42 +02:00 |
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Sebastien Bourdeauducq
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6a3c413717
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New bidirectional-capable Record API
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2013-04-01 21:53:33 +02:00 |
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Sebastien Bourdeauducq
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c4f4143591
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New CSR API
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2013-03-30 17:28:41 +01:00 |
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Sebastien Bourdeauducq
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b38818eb17
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examples/sim/fir: convert to new API
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2013-03-19 11:46:27 +01:00 |
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Sebastien Bourdeauducq
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af4eb02551
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examples/basic/arrays: demonstrate lowering of Array in Instance expression
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2013-03-18 18:37:23 +01:00 |
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Sebastien Bourdeauducq
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e2d156ef64
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genlib/cdc/MultiReg: remove idomain
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2013-03-15 19:49:24 +01:00 |
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Sebastien Bourdeauducq
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51bec340ab
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sim: remove PureSimulable (superseded by Module)
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2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
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208e039bbb
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Local clock domain example
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2013-03-15 18:18:32 +01:00 |
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Sebastien Bourdeauducq
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c99cc9343f
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examples/pytholite: use new APIs
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2013-03-12 16:59:24 +01:00 |
|
Sebastien Bourdeauducq
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907bfa87f4
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examples/basic: use new APIs
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2013-03-12 16:45:28 +01:00 |
|
Sebastien Bourdeauducq
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c2d54f481f
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examples/psync: cleanup
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2013-02-23 19:14:31 +01:00 |
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Sebastien Bourdeauducq
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6abac5907b
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examples/basic/psync: demonstrate the new features
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2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
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3a591c358c
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examples/fir: better filter
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2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
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38664d6e16
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fhdl: inline synthesis directive support
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2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
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dc93a231c6
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fhdl: tristate support
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2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
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92b67df41c
|
sim: default runner to Icarus Verilog
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2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
314a6c7743
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corelogic: complex arithmetic support
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2013-01-05 14:18:36 +01:00 |
|
Sebastien Bourdeauducq
|
4d0db2cb05
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examples/pytholite: fix imports
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2012-12-16 20:26:23 +01:00 |
|
Sebastien Bourdeauducq
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a67f483f0f
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Token: support idle_wait
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2012-12-14 19:16:22 +01:00 |
|
Sebastien Bourdeauducq
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6f99241585
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Move Token to migen.flow.transactions
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2012-12-14 15:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
a7227d7d2b
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Remove ActorNode
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2012-12-12 22:20:48 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
2a3ef28041
|
examples/sim/dataflow: update to new APIs
|
2012-11-28 22:44:14 +01:00 |
|
Sebastien Bourdeauducq
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39d577d65e
|
examples/dataflow/dma: update to new APIs
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2012-11-28 22:42:01 +01:00 |
|
Sebastien Bourdeauducq
|
7c4b5931bc
|
examples/basic: remove unroll example
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2012-11-28 22:16:02 +01:00 |
|
Sebastien Bourdeauducq
|
5440fa715c
|
examples/basic/arrays: add array assignment to fragment
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2012-11-26 22:47:35 +01:00 |
|
Sebastien Bourdeauducq
|
2418367c7a
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examples/sim/memory: do not use MemoryPort
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2012-11-26 18:19:10 +01:00 |
|
Sebastien Bourdeauducq
|
dac0d11e52
|
actorlib/sim: Dumper
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2012-11-24 00:00:07 +01:00 |
|
Sebastien Bourdeauducq
|
784a399431
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examples/memory: use new get_port API
|
2012-11-23 19:18:08 +01:00 |
|
Sebastien Bourdeauducq
|
7c6ebcf753
|
examples/pytholite/uio: demonstrate memories
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2012-11-23 16:24:20 +01:00 |
|
Sebastien Bourdeauducq
|
20d87682ad
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examples/pytholite/uio: simulate and convert Pytholite
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2012-11-23 13:10:40 +01:00 |
|
Sebastien Bourdeauducq
|
89643bc434
|
sim/ipc/Message: convert values
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2012-11-17 23:19:40 +01:00 |
|
Sebastien Bourdeauducq
|
6434ddd95a
|
examples/pytholite: add uio example
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2012-11-17 22:26:14 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
|
bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
748741b49a
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examples/pytholite/basic: demonstrate conversion to Verilog
|
2012-11-16 19:38:57 +01:00 |
|
Sebastien Bourdeauducq
|
7c7addbbe8
|
examples: basic Pytholite demo
|
2012-11-16 19:34:34 +01:00 |
|
Sebastien Bourdeauducq
|
daee4fb58c
|
transform/unroll_sync: autodetect in/out
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2012-10-15 20:32:07 +02:00 |
|
Sebastien Bourdeauducq
|
eacba52fba
|
transform/unroll: support for variables
|
2012-10-12 19:54:03 +02:00 |
|
Sebastien Bourdeauducq
|
e5fc9cc675
|
transform: unroll
|
2012-10-12 13:16:39 +02:00 |
|
Sebastien Bourdeauducq
|
e410973352
|
bank: support for atomic writes
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2012-10-08 18:43:18 +02:00 |
|
Sebastien Bourdeauducq
|
fc3187317b
|
examples: demonstrate multi-clock support
|
2012-09-10 23:46:19 +02:00 |
|
Sebastien Bourdeauducq
|
f7b1e67d08
|
examples: update LM32 instance
|
2012-09-10 23:45:27 +02:00 |
|
Sebastien Bourdeauducq
|
2a7d2908d1
|
examples: new namer
|
2012-09-09 19:34:46 +02:00 |