enjoy-digital
06a26b7c9b
Merge pull request #2003 from enjoy-digital/liteeth_wishbone_tx_rx_buses
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integration/soc/add_ethernet: Use separates TX/RX buses/regions for e…
2024-06-25 19:05:49 +02:00
Florent Kermarrec
14a640302c
integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac.
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LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161 .
2024-06-25 17:39:26 +02:00
Florent Kermarrec
1ad0f828bb
soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design.
2024-06-25 15:07:37 +02:00
Florent Kermarrec
462016a1d0
litex/tools/litex_json2dts_linux: Add initial CAN support.
2024-06-24 13:01:18 +02:00
Florent Kermarrec
71ff4eaadc
soc/cores/can: Switch to our fork of CTU-CAN-FD, remove debug signals and do a git clone if not present in execution directory.
2024-06-24 12:53:38 +02:00
Florent Kermarrec
bad64bcf6d
soc/cores: Add initial CTU-CAN-FD integration from 2021 work with recent updates/tests.
2024-06-24 12:27:17 +02:00
Florent Kermarrec
8afa36f24a
CHANGES.md: Update and add Issue/PR number.
2024-06-24 10:52:34 +02:00
enjoy-digital
a47dde6fbc
Merge pull request #1999 from FlyGoat/csr-re
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csr_bus: Honour re signal from the upstream bus
2024-06-24 10:36:48 +02:00
enjoy-digital
8e4f8781f7
Merge pull request #1996 from VOGL-electronic/litex_watchdog
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core: add watchdog feature
2024-06-24 10:32:48 +02:00
enjoy-digital
11537ec8cc
Merge pull request #2001 from rtucker85/master
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liblitespi: fix xor-used-as-pow bug
2024-06-24 09:05:34 +02:00
enjoy-digital
21674ee29c
Merge pull request #1998 from FlyGoat/ahb-fixes
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soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
2024-06-24 09:04:33 +02:00
Florent Kermarrec
fd5a01dd26
integration/soc: Cleanup #1997 .
2024-06-24 09:03:24 +02:00
enjoy-digital
5aad0d6aca
Merge pull request #1997 from FlyGoat/axi-id-fixes
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integration/soc: data_width_convert: Inherit more bus properties
2024-06-24 09:00:31 +02:00
Richard Tucker
a0763bf652
liblitespi: fix xor-used-as-pow bug
2024-06-24 16:37:36 +10:00
Jiaxun Yang
af3d2a29fc
csr_bus: Honour re signal from the upstream bus
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Currently CSR bus assumed that ~we means reading, that created
a problem that when for a CSR if reading has side effects and adr
parked unintentionally at that CSR, the reading side effect will be
triggered.
For SoCs, this happened when upstream bus issued a write transaction
with wishbone.sel, then on CSR bus it will be translated
as adr = addr, we = 0, which will be interpreted as a read to such
address, and trigger undesired side effect for such CSR.
Such upstream transaction will be generated by our bus width converter.
Given that we signal already presents in CSR Interface, the easiest way
to handle such situation is to generate re signal at bus bridges and
propagate it all the way down to the Interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 19:35:19 +01:00
Jiaxun Yang
9bdc22adfb
soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
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Don't do bus_addressing_convert as it's being handled in AHB2Wishbone
logic.
Add addressing parameters for AHBInterface constructor as required
by soc code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 16:18:26 +01:00
enjoy-digital
22f9c063db
Merge pull request #1949 from alexey-morozov/master
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The case when AWVALID and WVALID are not asserted at the same cycle
2024-06-23 09:03:17 +02:00
Jiaxun Yang
3d530e0b59
integration/soc: data_width_convert: Inherit more bus properties
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For data_width converter we need to ensure that adapted interface
have same properties as it's parent interface, so that id and user
signals for AXI will be propagated properly from parent to adapted
interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-22 17:54:41 +01:00
enjoy-digital
dd01a87653
Merge pull request #1993 from FlyGoat/jtag-patch
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Expand litex_sim JTAG support to more CPUs
2024-06-22 14:34:50 +02:00
Fin Maaß
0559f3f033
core: add watchdog feature
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Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-21 17:13:03 +02:00
enjoy-digital
29bdf6805f
Merge pull request #1840 from motec-research/parser_set_defaults_improvements
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Parser set defaults improvements
2024-06-21 10:52:09 +02:00
enjoy-digital
f40f63ae29
Merge pull request #1995 from VOGL-electronic/soc_spi_master_int
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soc: add_spi_master: make spi_clk_freq an int
2024-06-19 19:34:31 +02:00
Fin Maaß
447469b0aa
soc: add_spi_master: make spi_clk_freq an int
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convert spi_clk_freq to an int. this way the constant is also an int.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-19 16:29:35 +02:00
Gwenhael Goavec-Merou
d9854582c6
build/lattice/radiant: allows extra configuration (prj_set_strategy_value XX=YY) to be added at script creation time
2024-06-19 16:22:30 +02:00
enjoy-digital
d6b0c84f9c
Merge pull request #1992 from motec-research/fix_MockCSRRegion_base
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integration/export: Fix MockCSRRegion base definition.
2024-06-19 09:13:49 +02:00
enjoy-digital
e6353c8898
Merge pull request #1991 from motec-research/add_json_excludes
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Add json excludes
2024-06-19 09:12:22 +02:00
Florent Kermarrec
5a0fd6fb60
CHANGES.md: Update.
2024-06-19 09:07:22 +02:00
enjoy-digital
6fdf5a27d8
Merge pull request #1994 from trabucayre/zynqmp_peripheral_bus
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soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default
2024-06-19 08:48:03 +02:00
Gwenhael Goavec-Merou
146617eae8
soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default
2024-06-18 22:14:24 +02:00
Gwenhael Goavec-Merou
cc21c662ca
soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default
2024-06-18 19:46:56 +02:00
Jiaxun Yang
50c8ef07b6
jtagremote: Implement ntrst pin
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ntrst pin is critical to some JTAG taps to put tap
into a known state.
Implement it in jtagremote testbench with corresponding
remote bitbang commands and hook it up in litex_sim.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-18 14:49:43 +01:00
Florent Kermarrec
f46ef03f42
build/openfpgaloader: print command before executing it to ease debugging/manual tests.
2024-06-18 15:35:27 +02:00
Jiaxun Yang
a8b3f36592
soc/cores/cpu: Implement add_jtag method
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Implement add_jtag method for naxriscv, vexiiriscv and vexriscv_smp,
which is the de facto way to add JTAG ports to pads on other CPUs.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-18 14:14:52 +01:00
Gwenhael Goavec-Merou
63d72a87e6
soc/cores/cpu/zynqmp/core.py: added CAN over EMIO support
2024-06-18 12:26:36 +02:00
Gwenhael Goavec-Merou
0d1d378966
soc/cores/cpu/zynqmp/core.py: added interrupts support
2024-06-18 10:59:42 +02:00
Andrew Dennison
0f7ea96812
build/parser: detect invalid defaults
2024-06-18 09:37:31 +10:00
Andrew Dennison
4730ee2288
build/parser: support set_default(cpu_type="xxx")
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Ensures args_fill() for new cpu_type is called, allowing for patterns
in a target file like:
parser.set_defaults(cpu_type="vexriscv_smp")
parser.set_defaults(cpu_variant="linux")
parser.set_defaults(with_fpu=True)
2024-06-18 09:37:31 +10:00
Andrew Dennison
dad04eedef
integration/export: Fix MockCSRRegion base definition.
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MockCSR are not related to csr_base
2024-06-18 09:07:39 +10:00
Andrew Dennison
56c284e9bc
soc/integraion/builder: exclude some constants in add_json()
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Interrupt numbers from a downstream soc are not relevant in the main SOC
so exclude them by default.
2024-06-18 09:01:28 +10:00
Andrew Dennison
702761d789
soc/integraion/builder: fix variable names
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In _get_json_*() variable names were transposed in two places
resulting in confusing code with correct functionality.
2024-06-18 09:01:28 +10:00
Gwenhael Goavec-Merou
485341a1cf
soc/cores/cpu/zynq7000/core.py: fix missing CAN IO mode (security/nitpick)
2024-06-17 18:26:28 +02:00
Gwenhael Goavec-Merou
fba7ce42ec
soc/cores/cpu/zynq7000/core.py: PS CANx support with EMIO pads
2024-06-17 18:09:00 +02:00
Gwenhael Goavec-Merou
6c4a756655
soc/cores/cpu/zynq7000/core.py: added GPx tcl configuration
2024-06-17 17:18:24 +02:00
Gwenhael Goavec-Merou
1335d3cebc
soc/cores/cpu/zynq7000/core.py: enable F2P interrupts
2024-06-17 16:35:26 +02:00
Gwenhael Goavec-Merou
45928a3ce1
soc/cores/cpu/zynq7000/core.py: delayed filling ps7_tcl with config at finalize time
2024-06-17 16:29:23 +02:00
JoyBed
3f095a260d
Fix HP slave clock source and specify AXI version
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The absence of WID signal in AXI4 when compared to AXI3 can sometimes cause problems.
2024-06-17 16:16:07 +02:00
Florent Kermarrec
a899c23f65
soc/interconnect/packet: Add default values for HeaderField parameters.
2024-06-17 10:54:53 +02:00
Florent Kermarrec
81b70d1e37
soc/integration/builder: Only generate svd/memory.x export when specified (Since often not required and generation does not seems robust to all designs).
2024-06-14 14:58:06 +02:00
Florent Kermarrec
69008d7d5e
software/libbase/isr.c: Fix regression.
2024-06-14 14:08:22 +02:00
Florent Kermarrec
8278ff6622
software/libbase/isr.c: Generalize irq_table/attach/detach to all CPUS to have a common approach.
2024-06-14 12:08:52 +02:00