Commit Graph

1391 Commits

Author SHA1 Message Date
Robert Jordens 20b646bd1a add tool to build minimal xilinx toolchains 2015-03-27 19:21:47 +01:00
Florent Kermarrec ec080479da mibuild/sim: use the same architecture we use for others backends 2015-03-27 14:14:49 +01:00
Florent Kermarrec de31103cce platforms/minispartan6: add ftdi_fifo pins 2015-03-22 11:20:22 +01:00
Florent Kermarrec 200979fb81 platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz 2015-03-22 03:37:27 +01:00
Florent Kermarrec 7440ccd65b mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working) 2015-03-21 20:27:11 +01:00
Florent Kermarrec 1d2e7e8390 mibuild/platforms/minispartan6: adapt to recent changes (able to build simple example) 2015-03-21 18:31:50 +01:00
Florent Kermarrec 78b4f313bf mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25) 2015-03-21 18:28:09 +01:00
Florent Kermarrec 1a03c340c9 mibuild/platforms: review and fix small mistakes 2015-03-21 18:23:35 +01:00
Florent Kermarrec 3a38626556 mibuild/platforms: add minispartan6 (from Matt O'Gorman) 2015-03-21 18:22:26 +01:00
Robert Jordens 14b1da4018 test_actor: add unittests for SimActor
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements

* before, if the busy signal is never used, it is stripped
  and could not be accessed in simulation
2015-03-21 10:02:10 +01:00
Robert Jordens 5f045b7649 sim: keep track of unreferenced items
* items that are never referenced in any statements do not end up in the
namespace or in the verilog

* this memorizes items if they can not be found in the namespace and keeps
track of their values
2015-03-21 10:02:10 +01:00
Robert Jordens 4fe888702d pipistrello: switch is a button 2015-03-19 18:56:49 +01:00
Robert Jordens 47ea451315 pipistrello: compress and load bitstream at 6MHz 2015-03-19 18:48:45 +01:00
Robert Jordens 860b72c8b6 pipistrello: rename sdram->ddram 2015-03-19 18:48:22 +01:00
Sebastien Bourdeauducq 7fa1cd72a8 fhdl/verilog: fix dummy signal initial event 2015-03-19 00:24:30 +01:00
Florent Kermarrec 3aee58f484 mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented) 2015-03-18 18:54:22 +01:00
Florent Kermarrec 5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value;
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
Florent Kermarrec ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
Florent Kermarrec 2fc2f8a6c0 migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
2015-03-18 12:08:25 +01:00
Florent Kermarrec 89fefef3f8 genlib/io: add optional external rst to CRG 2015-03-17 16:22:22 +01:00
Florent Kermarrec 500e58ce7d mibuild/platform/versa: fix clock_constraints 2015-03-17 15:25:10 +01:00
Florent Kermarrec e07b7f632c mibuild/lattice: use ODDRXD1 and new synthesis directive 2015-03-17 14:59:36 +01:00
Florent Kermarrec b7d7fe1a4c fhdl/special: add optional synthesis directive (needed by Synplify Pro) 2015-03-17 14:59:05 +01:00
Florent Kermarrec 022ac26c22 mibuild/lattice: add LatticeAsyncResetSynchronizer 2015-03-17 12:42:36 +01:00
Florent Kermarrec c06ab82f13 mibuild/platforms/versa: add ethernet clock constraints 2015-03-17 12:04:00 +01:00
Florent Kermarrec ba2aeb08be mibuild/platforms/versa: add rst_n 2015-03-17 11:51:34 +01:00
Florent Kermarrec 6dd8d89c6c mibuild/lattice: fix LatticeDDROutput 2015-03-17 09:40:25 +01:00
Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
Florent Kermarrec e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
Florent Kermarrec b5a9909b08 mibuild/xilinx/common: add LatticeDDROutput 2015-03-16 22:57:18 +01:00
Florent Kermarrec 993059a59c mibuild/xilinx/common: add XilinxDDROutput 2015-03-16 22:53:05 +01:00
Florent Kermarrec 69ce6dd48c migen/genlib/io: add DDRInput and DDROutput 2015-03-16 22:47:13 +01:00
Florent Kermarrec b3b1209c62 mibuild/platforms: add ethernet to versa 2015-03-16 22:24:10 +01:00
Florent Kermarrec fab0b0b161 mibuild/platforms: add user_dip_btn to versa 2015-03-16 22:11:15 +01:00
Florent Kermarrec d6041879dd mibuild/lattice: use new Toolchain/Platform architecture 2015-03-16 21:24:21 +01:00
Florent Kermarrec e903b62af1 mibuild/altera: use new Toolchain/Platform architecture 2015-03-16 21:07:55 +01:00
Florent Kermarrec f7bfa13144 mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton) 2015-03-16 19:02:34 +01:00
Sebastien Bourdeauducq beeaefccea move pytholite to separate repos 2015-03-14 22:48:03 +01:00
Sebastien Bourdeauducq c824379878 fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
Sebastien Bourdeauducq aef9275c99 mibuild/xilinx: export special_overrides dictionary 2015-03-14 10:45:11 +01:00
Sebastien Bourdeauducq d34b7d7a6b mibuild/xilinx: remove obsolete CRG_DS 2015-03-14 00:27:24 +01:00
Sebastien Bourdeauducq 6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Sebastien Bourdeauducq 702d177c85 mibuild: get rid of Platform factory function, cleanup 2015-03-13 23:25:15 +01:00
Florent Kermarrec ff266bc2ee migen/genlib/io: add DifferentialOutput and Xilinx implementation 2015-03-12 19:30:57 +01:00
Florent Kermarrec bf28664cb4 genlib/io.py: fix copy/paste error (thanks rjo) 2015-03-12 18:49:49 +01:00
Florent Kermarrec c8ba8cde8e migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild 2015-03-12 18:38:53 +01:00
Florent Kermarrec 00e8616de2 mibuild/sim: clean up (thanks sb) 2015-03-10 16:41:52 +01:00
Sebastien Bourdeauducq 555c444da2 mibuild/sim/dut_tb: fix permissions 2015-03-10 11:06:55 +01:00