Sebastien Bourdeauducq
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6595b9a111
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actorlib/spi/SingleGenerator: export CSRs
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2013-07-13 17:12:51 +02:00 |
Sebastien Bourdeauducq
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9ab22fe3b1
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memtest/MemtestWriter: fix 'busy status stuck' bug
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2013-07-13 17:11:23 +02:00 |
Sebastien Bourdeauducq
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c2d6f14087
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flow/actor/PipelinedActor: clean up
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2013-07-12 18:52:34 +02:00 |
Florent Kermarrec
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3d899f04fd
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cif : fix 2x autorefresh in get_sdram_phy_header
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2013-07-12 15:39:14 +02:00 |
Sebastien Bourdeauducq
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6aa1e0c199
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actorlib/spi/DMAWriteController: len -> flen
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2013-07-11 19:22:56 +02:00 |
Sebastien Bourdeauducq
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379a48bb31
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software: add memtest
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2013-07-11 19:03:45 +02:00 |
Sebastien Bourdeauducq
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e42a42ce40
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software: move time.c to libbase
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2013-07-11 19:00:48 +02:00 |
Sebastien Bourdeauducq
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c2ec077d8f
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software: share SDRAM linker script
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2013-07-11 18:49:42 +02:00 |
Sebastien Bourdeauducq
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25506c1ab5
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software: share crt0
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2013-07-11 18:36:26 +02:00 |
Sebastien Bourdeauducq
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aa5cdd5e67
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make: add option to include memtest cores
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2013-07-11 18:32:05 +02:00 |
Sebastien Bourdeauducq
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be40cf178c
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top: integrate memtest cores
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2013-07-11 18:31:51 +02:00 |
Sebastien Bourdeauducq
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3162949f82
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memtest: add DMA cores
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2013-07-11 18:31:38 +02:00 |
Sebastien Bourdeauducq
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805432bec7
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memtest/LFSR: test bench
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2013-07-11 16:23:05 +02:00 |
Florent Kermarrec
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d3bbbded0f
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cif.py: use format instead of % in get_sdram_phy_header
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2013-07-11 10:08:21 +02:00 |
Sebastien Bourdeauducq
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a7a7cc0b95
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memtest: LFSR
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2013-07-10 21:08:57 +02:00 |
Sebastien Bourdeauducq
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26ff6f2a9c
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s6ddrphy: style and other minor fixes
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2013-07-10 20:39:53 +02:00 |
Florent Kermarrec
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f5ddd33e7e
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dfi: split phase description
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2013-07-10 19:56:47 +02:00 |
Florent Kermarrec
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60f1585fef
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use Migen s6ddrphy, generate sdram init_sequence in cif.py
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2013-07-10 19:56:09 +02:00 |
Sebastien Bourdeauducq
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9d9270b5cd
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dvisampler: report FIFO overflow
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2013-07-10 19:55:36 +02:00 |
Sebastien Bourdeauducq
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1d33c61308
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examples/sim/abstract_transactions_lasmi: check data
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2013-07-10 19:11:02 +02:00 |
Sebastien Bourdeauducq
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43fe16ef73
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bus/lasmibus: add separate req/data ack to target and initiator
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2013-07-10 19:09:51 +02:00 |
Sebastien Bourdeauducq
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af6ef0a3b4
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dma_lasmi/Writer: fix default FIFO depth
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2013-07-07 20:01:55 +02:00 |
Sebastien Bourdeauducq
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fa8112c3f5
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dma_lasmi/Reader: handle ack=1 when stb=0
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2013-07-07 18:57:05 +02:00 |
Sebastien Bourdeauducq
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7e6fbd31a4
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lasmibus/crossbar: simplify master ack generation
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2013-07-07 18:56:43 +02:00 |
Sebastien Bourdeauducq
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d0b21469e5
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make: fix byteswap invocation
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2013-07-07 14:55:06 +02:00 |
Sebastien Bourdeauducq
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b18cffb5e8
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xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior
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2013-07-04 23:49:12 +02:00 |
Sebastien Bourdeauducq
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05bc2885e9
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Call finalize() after CRG creation
|
2013-07-04 19:49:39 +02:00 |
Sebastien Bourdeauducq
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71c2c5813b
|
platforms/mixxeo: remove bank 3 DVI inputs
|
2013-07-04 19:27:28 +02:00 |
Sebastien Bourdeauducq
|
0883e99de3
|
Do not specify period constraints twice
|
2013-07-04 19:25:29 +02:00 |
Sebastien Bourdeauducq
|
0784cd164f
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Add Mixxeo platform
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2013-07-04 19:23:25 +02:00 |
Sebastien Bourdeauducq
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1f3c941a78
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platforms/m1: move generic platform commands to do_finalize
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2013-07-04 19:22:59 +02:00 |
Sebastien Bourdeauducq
|
4cd360e6e1
|
Mixxeo support
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2013-07-04 19:19:39 +02:00 |
Sebastien Bourdeauducq
|
eff7882721
|
dvisampler: support differential input
|
2013-07-04 19:18:24 +02:00 |
Sebastien Bourdeauducq
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b68c00d36f
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pytholite: fix kwargs handling
|
2013-07-03 17:20:05 +02:00 |
Sebastien Bourdeauducq
|
4096a785f9
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examples/pytholite/basic: demonstrate generator arguments
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2013-07-03 16:35:24 +02:00 |
Sebastien Bourdeauducq
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0aa58f5dcf
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pytholite: support generator arguments
|
2013-07-03 16:35:07 +02:00 |
Sebastien Bourdeauducq
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04efee7847
|
fhdl: mark variable as deprecated
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2013-06-30 20:14:20 +02:00 |
Sebastien Bourdeauducq
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6420b56908
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examples/complex: do not use variable
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2013-06-30 19:27:01 +02:00 |
Sebastien Bourdeauducq
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71b89e4c46
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fhdl/verilog: lower complex slices before reset insertion
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2013-06-30 14:32:47 +02:00 |
Sebastien Bourdeauducq
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ded5e569eb
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fhdl/tools: separate complex slice lowerer from basic lowerer
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2013-06-30 14:32:19 +02:00 |
Sebastien Bourdeauducq
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9c59ea1e26
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genlib/misc: remove bitreverse
|
2013-06-30 14:31:25 +02:00 |
Robert Jördens
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a255296171
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support re-slicing and non-unit step size
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
|
2013-06-30 14:03:34 +02:00 |
Robert Jördens
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9d241f8cd3
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coding.py: rewrite If() to make verilog more readable
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2013-06-30 11:39:47 +02:00 |
Sebastien Bourdeauducq
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b0d467d744
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pytholite: use eval instead of literal_eval
|
2013-06-28 19:03:55 +02:00 |
Robert Jördens
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ecc4062071
|
genlib/coding.py: binary vs. one-hot, priority coding
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2013-06-28 15:20:01 +02:00 |
Sebastien Bourdeauducq
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7e4552bbfc
|
lx9_microboard: improve compat with other boards
|
2013-06-27 19:30:57 +02:00 |
Robert Jordens
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c1cf37f05a
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add Avnet Spartan6 LX9 Micrboard platform
|
2013-06-27 19:18:47 +02:00 |
Robert Jordens
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e233c62d27
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* generic_platform.py: add a finalize() method
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
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2013-06-27 19:17:02 +02:00 |
Sebastien Bourdeauducq
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48a5b86dcd
|
genlib/cordic: cleanup
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2013-06-26 22:46:04 +02:00 |
Sebastien Bourdeauducq
|
080afdc3f9
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fhdl/verilog: fix signedness rules for comparison
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2013-06-26 22:45:47 +02:00 |