Sebastien Bourdeauducq
|
6595b9a111
|
actorlib/spi/SingleGenerator: export CSRs
|
2013-07-13 17:12:51 +02:00 |
|
Sebastien Bourdeauducq
|
9ab22fe3b1
|
memtest/MemtestWriter: fix 'busy status stuck' bug
|
2013-07-13 17:11:23 +02:00 |
|
Sebastien Bourdeauducq
|
c2d6f14087
|
flow/actor/PipelinedActor: clean up
|
2013-07-12 18:52:34 +02:00 |
Florent Kermarrec
|
3d899f04fd
|
cif : fix 2x autorefresh in get_sdram_phy_header
|
2013-07-12 15:39:14 +02:00 |
|
Sebastien Bourdeauducq
|
6aa1e0c199
|
actorlib/spi/DMAWriteController: len -> flen
|
2013-07-11 19:22:56 +02:00 |
|
Sebastien Bourdeauducq
|
379a48bb31
|
software: add memtest
|
2013-07-11 19:03:45 +02:00 |
|
Sebastien Bourdeauducq
|
e42a42ce40
|
software: move time.c to libbase
|
2013-07-11 19:00:48 +02:00 |
|
Sebastien Bourdeauducq
|
c2ec077d8f
|
software: share SDRAM linker script
|
2013-07-11 18:49:42 +02:00 |
|
Sebastien Bourdeauducq
|
25506c1ab5
|
software: share crt0
|
2013-07-11 18:36:26 +02:00 |
|
Sebastien Bourdeauducq
|
aa5cdd5e67
|
make: add option to include memtest cores
|
2013-07-11 18:32:05 +02:00 |
|
Sebastien Bourdeauducq
|
be40cf178c
|
top: integrate memtest cores
|
2013-07-11 18:31:51 +02:00 |
|
Sebastien Bourdeauducq
|
3162949f82
|
memtest: add DMA cores
|
2013-07-11 18:31:38 +02:00 |
|
Sebastien Bourdeauducq
|
805432bec7
|
memtest/LFSR: test bench
|
2013-07-11 16:23:05 +02:00 |
|
Florent Kermarrec
|
d3bbbded0f
|
cif.py: use format instead of % in get_sdram_phy_header
|
2013-07-11 10:08:21 +02:00 |
|
Sebastien Bourdeauducq
|
a7a7cc0b95
|
memtest: LFSR
|
2013-07-10 21:08:57 +02:00 |
|
Sebastien Bourdeauducq
|
26ff6f2a9c
|
s6ddrphy: style and other minor fixes
|
2013-07-10 20:39:53 +02:00 |
|
Florent Kermarrec
|
f5ddd33e7e
|
dfi: split phase description
|
2013-07-10 19:56:47 +02:00 |
|
Florent Kermarrec
|
60f1585fef
|
use Migen s6ddrphy, generate sdram init_sequence in cif.py
|
2013-07-10 19:56:09 +02:00 |
|
Sebastien Bourdeauducq
|
9d9270b5cd
|
dvisampler: report FIFO overflow
|
2013-07-10 19:55:36 +02:00 |
|
Sebastien Bourdeauducq
|
1d33c61308
|
examples/sim/abstract_transactions_lasmi: check data
|
2013-07-10 19:11:02 +02:00 |
|
Sebastien Bourdeauducq
|
43fe16ef73
|
bus/lasmibus: add separate req/data ack to target and initiator
|
2013-07-10 19:09:51 +02:00 |
|
Sebastien Bourdeauducq
|
af6ef0a3b4
|
dma_lasmi/Writer: fix default FIFO depth
|
2013-07-07 20:01:55 +02:00 |
|
Sebastien Bourdeauducq
|
fa8112c3f5
|
dma_lasmi/Reader: handle ack=1 when stb=0
|
2013-07-07 18:57:05 +02:00 |
|
Sebastien Bourdeauducq
|
7e6fbd31a4
|
lasmibus/crossbar: simplify master ack generation
|
2013-07-07 18:56:43 +02:00 |
|
Sebastien Bourdeauducq
|
d0b21469e5
|
make: fix byteswap invocation
|
2013-07-07 14:55:06 +02:00 |
|
Sebastien Bourdeauducq
|
b18cffb5e8
|
xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior
|
2013-07-04 23:49:12 +02:00 |
|
Sebastien Bourdeauducq
|
05bc2885e9
|
Call finalize() after CRG creation
|
2013-07-04 19:49:39 +02:00 |
|
Sebastien Bourdeauducq
|
71c2c5813b
|
platforms/mixxeo: remove bank 3 DVI inputs
|
2013-07-04 19:27:28 +02:00 |
|
Sebastien Bourdeauducq
|
0883e99de3
|
Do not specify period constraints twice
|
2013-07-04 19:25:29 +02:00 |
|
Sebastien Bourdeauducq
|
0784cd164f
|
Add Mixxeo platform
|
2013-07-04 19:23:25 +02:00 |
|
Sebastien Bourdeauducq
|
1f3c941a78
|
platforms/m1: move generic platform commands to do_finalize
|
2013-07-04 19:22:59 +02:00 |
|
Sebastien Bourdeauducq
|
4cd360e6e1
|
Mixxeo support
|
2013-07-04 19:19:39 +02:00 |
|
Sebastien Bourdeauducq
|
eff7882721
|
dvisampler: support differential input
|
2013-07-04 19:18:24 +02:00 |
|
Sebastien Bourdeauducq
|
b68c00d36f
|
pytholite: fix kwargs handling
|
2013-07-03 17:20:05 +02:00 |
|
Sebastien Bourdeauducq
|
4096a785f9
|
examples/pytholite/basic: demonstrate generator arguments
|
2013-07-03 16:35:24 +02:00 |
|
Sebastien Bourdeauducq
|
0aa58f5dcf
|
pytholite: support generator arguments
|
2013-07-03 16:35:07 +02:00 |
|
Sebastien Bourdeauducq
|
04efee7847
|
fhdl: mark variable as deprecated
|
2013-06-30 20:14:20 +02:00 |
|
Sebastien Bourdeauducq
|
6420b56908
|
examples/complex: do not use variable
|
2013-06-30 19:27:01 +02:00 |
|
Sebastien Bourdeauducq
|
71b89e4c46
|
fhdl/verilog: lower complex slices before reset insertion
|
2013-06-30 14:32:47 +02:00 |
|
Sebastien Bourdeauducq
|
ded5e569eb
|
fhdl/tools: separate complex slice lowerer from basic lowerer
|
2013-06-30 14:32:19 +02:00 |
|
Sebastien Bourdeauducq
|
9c59ea1e26
|
genlib/misc: remove bitreverse
|
2013-06-30 14:31:25 +02:00 |
Robert Jördens
|
a255296171
|
support re-slicing and non-unit step size
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
|
2013-06-30 14:03:34 +02:00 |
|
Robert Jördens
|
9d241f8cd3
|
coding.py: rewrite If() to make verilog more readable
|
2013-06-30 11:39:47 +02:00 |
|
Sebastien Bourdeauducq
|
b0d467d744
|
pytholite: use eval instead of literal_eval
|
2013-06-28 19:03:55 +02:00 |
|
Robert Jördens
|
ecc4062071
|
genlib/coding.py: binary vs. one-hot, priority coding
|
2013-06-28 15:20:01 +02:00 |
|
Sebastien Bourdeauducq
|
7e4552bbfc
|
lx9_microboard: improve compat with other boards
|
2013-06-27 19:30:57 +02:00 |
|
Robert Jordens
|
c1cf37f05a
|
add Avnet Spartan6 LX9 Micrboard platform
|
2013-06-27 19:18:47 +02:00 |
|
Robert Jordens
|
e233c62d27
|
* generic_platform.py: add a finalize() method
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
|
2013-06-27 19:17:02 +02:00 |
|
Sebastien Bourdeauducq
|
48a5b86dcd
|
genlib/cordic: cleanup
|
2013-06-26 22:46:04 +02:00 |
|
Sebastien Bourdeauducq
|
080afdc3f9
|
fhdl/verilog: fix signedness rules for comparison
|
2013-06-26 22:45:47 +02:00 |