1857ec6c32
fhdl/namer: support ClockSignal and ResetSignal. Closes #24
2015-09-22 14:30:16 +08:00
2c1553fea2
sim: insert resets, support ClockSignal and ResetSignal
2015-09-21 22:13:36 +08:00
99af825a5a
sim: drive clock signals
2015-09-21 21:53:41 +08:00
a67b4baa0c
sim: VCD output support
2015-09-21 21:20:31 +08:00
34ce6b077f
verilog: remove unneeded import
2015-09-21 21:19:58 +08:00
1767eef9cb
fhdl/visit: support Constant
2015-09-20 16:10:17 +08:00
7f767095ec
sim: support generators yielding statements
2015-09-20 15:04:15 +08:00
320dffb4ac
sim: memory access from generators
2015-09-20 14:52:26 +08:00
59802bec76
fhdl/structure: add missing init
2015-09-20 14:46:30 +08:00
8bbfaa01fc
sim: memory support
2015-09-19 23:21:46 +08:00
1861ae9d01
fhdl/specials: MemoryPort.clock should always be a ClockSignal
2015-09-19 23:21:24 +08:00
262fd50677
fhdl/simplify: add MemoryToArray
2015-09-19 23:20:57 +08:00
944a0b0480
test/fifo: convert to new API
2015-09-19 23:20:30 +08:00
dcf4f7fef3
genlib/fifo: add missing import
2015-09-19 23:20:19 +08:00
9420aabc0d
sim: support arrays, and cat+slice in assignment target
2015-09-19 14:56:26 +08:00
563231fdfb
migen/genlib/cdc: fix BusSynchronizer
...
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.
This fix add a timeout to detect such situation and create another token.
2015-09-19 12:21:54 +08:00
bfcc8f9661
sim: remove unneeded import
2015-09-19 12:18:20 +08:00
84f98b4632
genlib/CRG: fix variable name conflict
2015-09-19 11:18:44 +08:00
0a55ef5bc3
test: add divider
2015-09-18 11:07:14 +08:00
ec1d4edf84
sim: support Case
2015-09-17 17:25:06 +08:00
9d3fd50950
sim: variables are deprecated
2015-09-17 17:24:57 +08:00
2688d66ea1
sim: fix comb evaluation
2015-09-17 17:24:20 +08:00
049a8f082a
test/size: do not test removed functions
2015-09-17 17:23:19 +08:00
4a3a1bc5b0
test/coding: use new API
2015-09-17 17:22:59 +08:00
12cd390c0b
genlib/misc: add missing import
2015-09-17 17:22:44 +08:00
776579f0d7
fhdl/structure: all case statements should be lists
2015-09-17 17:22:24 +08:00
bcf62997f6
fhdl/bitcontainer: remove fiter
2015-09-17 17:22:03 +08:00
c2109f8f81
minor bugfixes
2015-09-17 15:20:27 +08:00
6e08df75ee
sim: support eval of slice, cat and mux
2015-09-17 14:39:36 +08:00
9dd3200ba2
fhdl/structure: fix namespace pollution
2015-09-17 14:39:17 +08:00
6569c516a1
test: bit reverse
2015-09-17 14:38:55 +08:00
0a92e346d3
fhdl/bitcontainer: remove fslice and freversed
2015-09-17 14:38:33 +08:00
fd88b9b8a3
test/constant: use new API
2015-09-17 11:08:40 +08:00
74c9159a01
add unittests for Constant
2015-09-17 11:06:04 +08:00
f5ab734bdf
fhdl/verilog: fix case value sort
2015-09-17 08:03:48 +08:00
e940c6d9b9
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
2015-09-15 12:38:02 +08:00
42afba2bbc
fhdl/decorators: remove traces of deprecated API
2015-09-12 19:44:35 +08:00
eb921fb957
genlib: remove reverse_bytes, FlipFlop, Counter
2015-09-12 19:40:29 +08:00
9667d61e84
genlib: cleanup CRG
2015-09-12 19:40:07 +08:00
1bdb9bee22
fhdl/decorators: remove deprecated API
2015-09-12 19:34:44 +08:00
336728413a
simplify imports, migen.fhdl.std -> migen
2015-09-12 19:34:07 +08:00
b43495aab1
build/xilinx: minor cleanup
2015-09-12 16:48:25 +08:00
047d1f48b5
test/support,signed,sort: use new simulator
2015-09-12 16:28:21 +08:00
8ee361ffe2
sim: refactor comb commit
2015-09-12 16:27:59 +08:00
5fa7f7414f
sim: support eval of nested lists
2015-09-12 16:01:53 +08:00
9556c335ea
genlib/sort: remove unneeded import
2015-09-12 15:21:42 +08:00
fa6d96bb9a
test/examples: do not attempt to run deleted examples
2015-09-12 15:13:45 +08:00
7bd72a16df
sim: support clock domains without sync
2015-09-12 15:12:57 +08:00
fd986210f8
simulator: support generators
2015-09-10 21:44:14 -07:00
10d89d81f4
new simulator: basic execution
2015-09-10 20:33:45 -07:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens