Commit Graph

142 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 1d33c61308 examples/sim/abstract_transactions_lasmi: check data 2013-07-10 19:11:02 +02:00
Sebastien Bourdeauducq 4096a785f9 examples/pytholite/basic: demonstrate generator arguments 2013-07-03 16:35:24 +02:00
Sebastien Bourdeauducq 6420b56908 examples/complex: do not use variable 2013-06-30 19:27:01 +02:00
Robert Jördens a255296171 support re-slicing and non-unit step size
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
2013-06-30 14:03:34 +02:00
Sebastien Bourdeauducq d0caa738bd FSM: new API 2013-06-25 22:17:39 +02:00
Sebastien Bourdeauducq 9f560cb758 examples/sim: add LASMI demo 2013-06-09 23:36:51 +02:00
Sebastien Bourdeauducq 2948f6a16a examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI 2013-06-09 14:17:30 +02:00
Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq 70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq 746e452838 actorlib/dma_asmi: support for writes 2013-04-28 18:06:36 +02:00
Sebastien Bourdeauducq 6c08cd67aa graycounter: expose binary output 2013-04-25 13:11:15 +02:00
Sebastien Bourdeauducq 0f9df2d732 genlib: add Gray counter 2013-04-24 19:13:36 +02:00
Florent Kermarrec f599fe4ade Support for resetless clock domains 2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq 72ef4b9683 ioo+pytholite: use new Module API 2013-04-10 23:42:46 +02:00
Sebastien Bourdeauducq 746acdacd1 ioo: move to genlib 2013-04-10 22:28:53 +02:00
Sebastien Bourdeauducq 692794a21f flow: use Module and new Record APIs 2013-04-10 19:12:42 +02:00
Sebastien Bourdeauducq 6a3c413717 New bidirectional-capable Record API 2013-04-01 21:53:33 +02:00
Sebastien Bourdeauducq c4f4143591 New CSR API 2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq b38818eb17 examples/sim/fir: convert to new API 2013-03-19 11:46:27 +01:00
Sebastien Bourdeauducq af4eb02551 examples/basic/arrays: demonstrate lowering of Array in Instance expression 2013-03-18 18:37:23 +01:00
Sebastien Bourdeauducq e2d156ef64 genlib/cdc/MultiReg: remove idomain 2013-03-15 19:49:24 +01:00
Sebastien Bourdeauducq 51bec340ab sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq 208e039bbb Local clock domain example 2013-03-15 18:18:32 +01:00
Sebastien Bourdeauducq c99cc9343f examples/pytholite: use new APIs 2013-03-12 16:59:24 +01:00
Sebastien Bourdeauducq 907bfa87f4 examples/basic: use new APIs 2013-03-12 16:45:28 +01:00
Sebastien Bourdeauducq c2d54f481f examples/psync: cleanup 2013-02-23 19:14:31 +01:00
Sebastien Bourdeauducq 6abac5907b examples/basic/psync: demonstrate the new features 2013-02-23 19:04:11 +01:00
Sebastien Bourdeauducq 3a591c358c examples/fir: better filter 2013-02-22 23:19:56 +01:00
Sebastien Bourdeauducq f9acee4e68 corelogic -> genlib 2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq 38664d6e16 fhdl: inline synthesis directive support 2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq 49cfba50fa New 'specials' API 2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq dc93a231c6 fhdl: tristate support 2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq 92b67df41c sim: default runner to Icarus Verilog 2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq 314a6c7743 corelogic: complex arithmetic support 2013-01-05 14:18:36 +01:00
Sebastien Bourdeauducq 4d0db2cb05 examples/pytholite: fix imports 2012-12-16 20:26:23 +01:00
Sebastien Bourdeauducq a67f483f0f Token: support idle_wait 2012-12-14 19:16:22 +01:00
Sebastien Bourdeauducq 6f99241585 Move Token to migen.flow.transactions 2012-12-14 15:55:38 +01:00
Sebastien Bourdeauducq a7227d7d2b Remove ActorNode 2012-12-12 22:20:48 +01:00
Sebastien Bourdeauducq d8e478efee Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
Sebastien Bourdeauducq 50ed73c937 New specification for width and signedness 2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq 2a3ef28041 examples/sim/dataflow: update to new APIs 2012-11-28 22:44:14 +01:00
Sebastien Bourdeauducq 39d577d65e examples/dataflow/dma: update to new APIs 2012-11-28 22:42:01 +01:00
Sebastien Bourdeauducq 7c4b5931bc examples/basic: remove unroll example 2012-11-28 22:16:02 +01:00
Sebastien Bourdeauducq 5440fa715c examples/basic/arrays: add array assignment to fragment 2012-11-26 22:47:35 +01:00
Sebastien Bourdeauducq 2418367c7a examples/sim/memory: do not use MemoryPort 2012-11-26 18:19:10 +01:00
Sebastien Bourdeauducq dac0d11e52 actorlib/sim: Dumper 2012-11-24 00:00:07 +01:00
Sebastien Bourdeauducq 784a399431 examples/memory: use new get_port API 2012-11-23 19:18:08 +01:00
Sebastien Bourdeauducq 7c6ebcf753 examples/pytholite/uio: demonstrate memories 2012-11-23 16:24:20 +01:00
Sebastien Bourdeauducq 20d87682ad examples/pytholite/uio: simulate and convert Pytholite 2012-11-23 13:10:40 +01:00
Sebastien Bourdeauducq 89643bc434 sim/ipc/Message: convert values 2012-11-17 23:19:40 +01:00