Florent Kermarrec
225a518f7e
soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.
2021-03-04 08:40:47 +01:00
Vamsi Vytla
ae5f67f6f0
litex/soc/cores/ussysmon.py: minor bug
2021-03-03 14:47:52 -08:00
Vamsi Vytla
1793efb50b
litex/soc/cores/ussysmon.py: dadr address space bump
2021-03-03 14:38:27 -08:00
Florent Kermarrec
ccc8916995
soc/cores/video: Add initial (and simple) VideoFrameBuffer core.
2021-03-03 19:58:11 +01:00
Vamsi Vytla
922f85e64b
litex/soc/cores/ussysmon.py: ADC transfer function
2021-03-03 10:50:58 -08:00
Florent Kermarrec
24fb153fa1
soc/integration: Add add_video_terminal method to LiteXSoC.
...
Adds the new LiteX's VideoTerminal core to the SoC:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
2021-03-03 17:45:02 +01:00
Florent Kermarrec
35ffba8801
soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.
2021-03-03 16:17:12 +01:00
Florent Kermarrec
c5ee6741a0
software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).
2021-03-03 11:32:43 +01:00
Florent Kermarrec
d3407c67b1
build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.
2021-03-03 09:25:54 +01:00
Florent Kermarrec
134c628357
cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.
2021-03-03 09:15:51 +01:00
Florent Kermarrec
61dcd1e8fd
soc/cores/led: Minor cosmetic cleanups.
2021-03-03 09:02:41 +01:00
Florent Kermarrec
19b1e50cbd
soc/cores/icap: Minor cosmetic cleanups.
2021-03-03 09:01:41 +01:00
Florent Kermarrec
e6f1d677e7
soc/cores/freqmeter: Minor cosmetic cleanups.
2021-03-03 08:59:51 +01:00
Florent Kermarrec
ce5e3e3b93
soc/cores/ecc: Minor cosmetic cleanups.
2021-03-03 08:55:37 +01:00
Florent Kermarrec
2fd7451fc9
soc/cores/code_8b10b: Minor cosmetic cleanups.
2021-03-03 08:54:31 +01:00
Florent Kermarrec
2e531e0ec7
soc/cores/dna: Add separator/comment.
2021-03-03 08:49:47 +01:00
Vamsi Vytla
71f7ce6a57
soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices
2021-03-02 20:31:52 -08:00
enjoy-digital
c23e8813fc
Merge pull request #836 from hplp/master
...
demo with c++ HW example
2021-03-02 09:13:10 +01:00
Sergiu Mosanu
7fd39235af
Merge pull request #1 from hplp/cppdemo
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demo with basic C and C++ examples
2021-03-02 01:31:46 -05:00
Sergiu Mosanu
769f36d468
extend demo with basic C and C++ examples
2021-03-02 01:28:21 -05:00
enjoy-digital
415bf63594
Merge pull request #830 from dayjaby/vexriscv_mem_map
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VexRiscv: More general mem_map
2021-03-01 11:15:56 +01:00
David Jablonski
ceb8a6502c
VexRiscv: More general mem_map
2021-02-25 10:36:43 +01:00
Florent Kermarrec
6e883b4513
tools/litex_sim: Add boot to main_ram when sdram_init contents provided.
2021-02-25 09:10:26 +01:00
Florent Kermarrec
8f5d2ba27f
tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided.
...
This avoid corrupting pre-initialized contents or disabling memtest manually.
2021-02-25 09:06:26 +01:00
Florent Kermarrec
80bd4ac4ec
bios: Add boot command to be able to boot directly from system memory.
...
This is useful for un-usual boot sequences where the binaries are not
loaded directly by the BIOS but externally (over a bridge for example).
Example of use:
$litex_sim
$litex_bare_metal_demo --build-path=build/sim
$litex_sim --ram-init=demo.bin
Press Esc during the LiteX boot.
litex> help
LiteX BIOS, available commands:
flush_cpu_dcache - Flush CPU data cache
crc - Compute CRC32 of a part of the address space
ident - Identifier of the system
help - Print this help
serialboot - Boot from Serial (SFL)
romboot - Boot from ROM
reboot - Reboot
boot - Boot from Memory
mem_speed - Test memory speed
mem_test - Test memory access
mem_copy - Copy address space
mem_write - Write address space
mem_read - Read address space
mem_list - List available memory regions
litex>
litex> mem_list
Available memory regions:
ROM 0x00000000 0x8000
SRAM 0x01000000 0x2000
MAIN_RAM 0x40000000 0x10000000
CSR 0x82000000 0x10000
litex>
litex> boot 0x40000000
Executing booted program at 0x40000000
--============= Liftoff! ===============--
LiteX minimal demo app built Feb 24 2021 11:30:05
Available commands:
help - Show this command
reboot - Reboot CPU
donut - Spinning Donut demo
litex-demo-app>
2021-02-24 11:41:01 +01:00
enjoy-digital
c18ea700cc
Merge pull request #822 from antmicro/bios-dynamic-ip
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software/bios: add an option to change ip and mac address in runtime
2021-02-24 09:27:48 +01:00
Aleksandra Swierkowska
7abd66d710
bios/boot: add functions changing local and remote IP in runtime
2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska
1c8df130b4
integration/soc.py: add parameter dynamic_ip to add_ethernet
2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska
fc6b02d0da
libliteeth/udp: add udp_set_ip and udp_set_mac functions
2021-02-23 20:52:43 +01:00
Florent Kermarrec
91cebb5159
cpu/microwatt: Set XICS_ICS's SRC_NUM to 16.
...
Expected to be 16 in xics.vhdl: assert SRC_NUM = 16 report "Fixup address decode with log2";
2021-02-22 10:57:31 +01:00
Florent Kermarrec
a51bf60712
cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).
2021-02-22 10:31:08 +01:00
enjoy-digital
d5c2f6760c
Merge pull request #824 from scanakci/blackparrot_litex
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Update BlackParrot Readme
2021-02-22 10:23:25 +01:00
Tim Ansell
5a89808fcd
Merge pull request #823 from RobertWilbrandt/svd_export_constants
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soc/integration/export Add constants to SVD export
2021-02-21 08:22:57 -08:00
sadullah
96d9971abe
Update BlackParrot Readme
2021-02-20 22:58:34 -05:00
Robert Wilbrandt
251cea5647
Add constants to SVD export
2021-02-20 21:16:45 +01:00
Florent Kermarrec
7513460572
integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required.
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When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi
will allow disabling MSI when set to False.
2021-02-19 11:35:49 +01:00
Florent Kermarrec
d4edc132c1
tools/remote/comm_pcie: fix typo.
2021-02-19 10:33:04 +01:00
Florent Kermarrec
b47160c74e
tools/litex_term: replace CrossoverUART with BridgeUART for more genericity, rework bridge/jtag args.
...
The CrossoverUART was in fact a particular UART connected to a second UART. Being able
to have access to multiple UARTs over a Bridge can be useful for several purposes, ex:
SoC0 --> UART0 + JTAGBone + litex_term bridge --bridge-name=UART0
SoC1 --> UART1 +--> SoC --> UARTBone --> LiteX-Server + litex_term bridge --bridge-name=UART1
SoC2 --> UART2 + EtherBone + litex_term bridge --bridge-name=UART2
2021-02-18 18:02:05 +01:00
Florent Kermarrec
6ac410a462
cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term.
2021-02-18 17:55:53 +01:00
Florent Kermarrec
fc83a9281a
interconnect/csr: remove address wrapping within a CSRBank.
...
To minimize logic, decoding inside a CSRBank to limited to the CSRs inside
the bank and could wraps since partially decoded:
For example, accessing SoCController on addresses still on the CSRBank defined
for real CSRs produced:
litex> mem_read 0x82000000 128
Memory dump:
0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000010 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000020 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000030 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000040 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000050 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000060 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000070 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
This is generally not an issue on most of the systems, but it could confuse user
or produce un-wanted behaviour when bus data-width converter are used.
With this change, the address is fully decoded, which removes the address wrapping:
litex> mem_read 0x82000000 128
Memory dump:
0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4.........
0x82000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0x82000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Resource usage increase seems minimal.
2021-02-18 14:44:50 +01:00
Florent Kermarrec
12bdf43958
soc/cores/ecc: cosmetic cleanups.
2021-02-18 10:00:27 +01:00
Florent Kermarrec
7ce5aef428
soc/cores/led: add add_pwm method to allow adjusting brightness dynamically (or not).
...
LedChaser without PWM:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
Add PWM to it (with default values: 50% duty cycle):
self.leds.add_pwm()
Add PWM with custom default values (25% duty cycle here):
self.leds.add_pwm(default_width=128, default_period=1024)
Then adjust brightness dynamically from the BIOS or your software:
$cat csr.csv:
csr_register,leds_out,0x82003000,1,rw
csr_register,leds_pwm_enable,0x82003004,1,rw
csr_register,leds_pwm_width,0x82003008,1,rw
csr_register,leds_pwm_period,0x8200300c,1,rw
Set PWM to 0%:
$mem_write 0x82003008 0
Set PWM to 25%:
$mem_write 0x82003008 256
Set PWM to 50%:
$mem_write 0x82003008 512
Set PWM to 75%:
$mem_write 0x82003008 768
Set PWM to 100%:
$mem_write 0x82003008 1024
You can also only use default values and disable CSR is dynamic configuration is not
required (with_csr=False) or adjust PWM period if want to use a specific PWM period
in your system.
2021-02-18 09:47:30 +01:00
Florent Kermarrec
fc282b3084
soc/cores/pwm: add configurable default enable/width/period values.
2021-02-18 09:39:18 +01:00
Florent Kermarrec
908e72e65b
cores/uart: rewrite RS232PHYTX/RX (with FSM and comments) and optimize resource usage (~100LCs).
2021-02-17 15:04:14 +01:00
enjoy-digital
7c7f540488
Merge pull request #821 from jersey99/master
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build/xilinx/vivado.py: Allow a tcl script to be added as ip
2021-02-17 08:12:09 +01:00
Florent Kermarrec
82c1f5dccb
litex_setup/ibex: add pythondata-misc-opentitan to litex_setup and use it for Ibex CPU.
2021-02-17 08:07:07 +01:00
Florent Kermarrec
285bb96278
cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default.
...
Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).
2021-02-16 20:00:43 +01:00
Florent Kermarrec
9a8a8c0fe5
software/liblitedram: remove SDRAM_PHY_WRITE_LEVELING_REINIT no longer required on Ultrascale(+).
2021-02-16 16:26:34 +01:00
Vamsi Vytla
385dec8560
Merge remote-tracking branch 'upstream/master'
2021-02-15 09:29:47 -08:00
Vamsi Vytla
1fde282291
build/xilinx/vivado.py: Allow a tcl script to be added as ip. These tcl scripts tend to generate .xci's on the fly. The tcl script can be looked up in the vivado console as the ip is generated
2021-02-15 09:29:00 -08:00