3e30c64842
litex_setup: add litex-boards
2019-08-26 09:28:58 +02:00
d79cd87dd6
Merge pull request #246 from gsomlo/gls-native-rv64
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software: use native toolchain for same host, target architectures
2019-08-23 21:36:51 +02:00
6d844a038a
software: use native toolchain for same host, target architectures
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LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-23 09:04:55 -04:00
d36f1fb7d2
Merge pull request #244 from atommann/master
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changing http to https
2019-08-17 11:54:39 +02:00
a45dbee54f
changing http to https
2019-08-17 16:02:10 +08:00
92e5b4b2cd
Merge pull request #2 from enjoy-digital/master
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update with hyperram and other changes
2019-08-16 14:36:59 +02:00
4990bf33c0
soc/core: simplify/cleanup HyperRAM core
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- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
f47e4978f2
libero enable enhanced constraints
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Libero 12.0 does not support any more classic constraint flow
2019-08-16 10:31:53 +02:00
d1502d4195
soc/cores: add initial simple hyperram core
2019-08-16 09:48:17 +02:00
6e6fe83af3
build/altera/quartus: add add_ip method to use Quartus QSYS files
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platform.add_ip("my_ip.qsys")
2019-08-15 13:45:29 +02:00
2899928aba
cpu_interface: add json csr map export, simplify csv csr map export using json
2019-08-15 09:27:33 +02:00
9d4b7cd515
bios/sdram: set init done after memtest (for standalone LiteDRAM controllers)
2019-08-14 19:09:58 +02:00
0cd4e45f48
build/xilinx/vivado: use "" for strings
2019-08-14 19:03:10 +02:00
8d161a47cf
build/xilinx/vivado: remove with_phys_opt
2019-08-14 19:02:01 +02:00
f6638ded13
Merge pull request #243 from sergachev/master
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build/xilinx/vivado: improve directive support
2019-08-14 18:58:15 +02:00
ccc2cbd9d4
Merge pull request #241 from railnova/zynq
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[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 18:55:34 +02:00
861eea8a07
build/xilinx/vivado: improve directive support
2019-08-14 17:49:13 +02:00
db4c609a33
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 11:30:39 +02:00
6d5fddc160
cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
2019-08-14 07:35:45 +02:00
383c05e239
Merge pull request #240 from danielkucera/patch-1
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more understandable error when missing a memory
2019-08-13 10:34:50 +02:00
a5eaf172c5
more understandable error when missing a memory
2019-08-13 10:14:16 +02:00
1d957d7a31
Update .gitmodules
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http to https
2019-08-12 22:20:34 +08:00
2b815f7096
Merge pull request #235 from gsomlo/gls-trellis-yosys-opt
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build/lattice/trellis: use additional yosys optimization flags
2019-08-10 15:33:05 +02:00
6c298cb708
build/lattice/trellis: use abc9 techmapping pass with yosys
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-09 09:12:22 -04:00
31bfb54667
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys
2019-08-09 13:26:31 +02:00
e670cb9176
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
2019-08-09 12:33:10 +02:00
6d94c07d70
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
2019-08-09 10:33:42 +02:00
0c287b11ba
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
2019-08-09 09:27:32 +02:00
82cd557c24
software/bios: add Ethernet PHY MDIO read/write/dump commands
2019-08-09 09:26:41 +02:00
0ba9ab92b4
altera/common: fix AsyncResetSynchronizer polarity and simplify
2019-08-08 16:19:22 +02:00
124dff8f3f
build/xilinx/common: improve presentation
2019-08-08 16:08:55 +02:00
60873a5b73
microsemi/common: improve presentation
2019-08-08 16:06:40 +02:00
36d9d78c5e
build/altera/common: improve presentation
2019-08-08 16:02:34 +02:00
95953d2928
platforms/default_clk_period: use 1e9/freq
2019-08-07 08:36:04 +02:00
f1d8c70bd8
targets/minispartan6/crg: only keep S6PLL code
2019-08-07 08:29:59 +02:00
d3d0a6231c
cores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 08:29:20 +02:00
a881817fb3
cores/clock/s6pll: add phase support
2019-08-07 08:18:54 +02:00
6b7ca0cff7
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
2019-08-07 08:17:44 +02:00
1884649de1
litex_term: make sure to unconfigure console when board is unplugged
2019-08-06 08:46:25 +02:00
e052d7f645
soc/integration/builder: -x
2019-08-06 07:56:45 +02:00
236070fdcf
cores: -x on spi.py
2019-08-05 10:36:43 +02:00
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
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Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
ce5c58592b
soc/cores/uart: add FT245 FIFO mode support (sync & async)
2019-08-04 12:22:35 +02:00
a496760cb6
build/altera/quartus: use .bat on win32/cygwin
2019-08-02 10:27:38 +02:00
7e0ea07076
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning
2019-08-01 21:03:05 +02:00
92d93ad221
cores/pwm: remove default CSR reset values.
2019-07-29 08:38:28 +02:00
25ca0a8b71
soc: generate git header and show migen/litex git sha1 in bios
2019-07-27 20:27:53 +02:00
ae00482dde
Merge pull request #223 from sergachev/master
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support vivado incremental implementation
2019-07-25 20:24:25 +02:00
fdb119cb7b
support vivado incremental implementation
2019-07-25 19:18:11 +02:00
e637aa657b
Merge pull request #222 from antmicro/bump_vexriscv
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cpu/vexriscv: bump submodule
2019-07-25 09:25:26 +02:00
Florent Kermarrec
Gabriel L. Somlo
atommann
Antti Lukats
Ilia Sergachev
chmousset
Daniel Kucera
Ilia Sergachev