932475a29b
cpu/vexriscv: bump submodule
2019-07-25 08:43:35 +02:00
bc7ab637dd
bios/sdram: fix compilation warning
2019-07-25 07:46:14 +02:00
a7895e4982
test/test_axi: remove use of rand_wait, rename rand_level to random
2019-07-23 21:02:09 +02:00
1cfb36e1e4
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)
2019-07-23 20:35:28 +02:00
556d2c7c0f
Merge pull request #221 from antmicro/bump_vexriscv
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cpu/vexriscv: bump submodule
2019-07-23 12:01:13 +02:00
3e89c56468
cpu/vexriscv: bump submodule
2019-07-23 11:49:18 +02:00
e673fce445
bios/boot: fix default EMULATOR_RAM_BASE
2019-07-23 10:28:19 +02:00
0acacbaa82
cores/clock: cleanup
2019-07-23 09:54:30 +02:00
edf8aa8cfd
cores/clock: add initial iCE40 support
2019-07-23 09:27:20 +02:00
6d54335839
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
2019-07-22 21:55:07 +02:00
462d12bacc
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
2019-07-22 21:54:24 +02:00
fc12961e7e
soc_core: fix cpu_variant definition
2019-07-22 12:46:39 +02:00
af61688d1d
bios/boot: fix booting rework
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- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
2019-07-22 11:47:41 +02:00
4b686dbdb2
soc_core: fix cpu_variant config (we don't want the extension)
2019-07-22 11:44:32 +02:00
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
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Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
95cfd0b9e5
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)
2019-07-22 10:28:03 +02:00
bfdcf4b2a0
platforms/versa_ecp5: add spiflash pads
2019-07-22 10:25:55 +02:00
41eb21b343
soc_core: optimize mem_decoder
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Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220 ), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.
The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
2019-07-22 08:53:54 +02:00
0eff65bb31
cores/up5ksram: optimize bus.adr decoding
2019-07-22 07:55:47 +02:00
bb99c4685a
cores/up5kspram: simplify and add support for all width/depth configurations
2019-07-21 19:28:31 +02:00
eaf84b8581
cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional
2019-07-20 12:57:32 +02:00
ea619e3afe
cores/spi: rename add_control paramter to add_csr
2019-07-20 12:56:37 +02:00
ec411a6ac1
soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs
2019-07-20 12:52:44 +02:00
bca42f742c
Merge pull request #219 from flammit/fix-ecp5-pll
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soc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-07-16 07:48:22 +02:00
8335f13fb1
bios/boot: rework netboot/flashboot for VexRiscv in linux variant
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Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.
Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.
2019-07-15 16:02:58 +02:00
a19bdd0e6a
soc_core: generate extra string-based config defines
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C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.
2019-07-15 15:58:54 +02:00
005c07769b
soc_core: include information about cpu variant in csv and headers
2019-07-15 15:58:54 +02:00
c6c743915a
soc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-07-14 12:27:28 -07:00
d3aaaf5e6c
cores/spi: fix/simplify loopback
2019-07-13 13:10:27 +02:00
59fda8da93
README: update banner
2019-07-13 13:04:00 +02:00
769d15d433
cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test
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Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
2019-07-13 12:55:19 +02:00
ee8fec10ff
soc/cores: add ECC (Error Correcting Code)
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Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
2019-07-13 11:44:29 +02:00
7dbddb3a56
platforms/tinyfpga_bx: add serial extension
2019-07-13 11:43:16 +02:00
831a191698
README: add a few links to papers/presentations/tutorials
2019-07-12 20:11:44 +02:00
95796c5b29
Merge pull request #218 from railnova/zynq
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[fix] Slave interface HP0 clk name
2019-07-12 18:00:03 +02:00
dcf55ad4f3
[fix] Slave interface HP0 clk name
2019-07-12 16:37:23 +02:00
08772fc0c9
Merge pull request #217 from sergachev/master
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spi: change CSR to CSRStorage
2019-07-12 14:44:53 +02:00
dacec6aa86
spi: change CSR to CSRStorage
2019-07-12 14:12:51 +02:00
be280bed5e
soc_zynq: use zynq fabric reset as sys reset
2019-07-12 09:52:50 +02:00
220f43753b
soc_zynq: add missing axi hp0 clock
2019-07-10 16:51:08 +02:00
9c8c037108
soc_zynq: move axi gp0 clock connection to add_gp0 method
2019-07-10 16:50:06 +02:00
b0192e5f8b
soc_core: use fixed 16MB CSR address space
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Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
2019-07-10 10:39:00 +02:00
68a503174c
soc_sdram: limit main_ram to 512MB for now
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Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
2019-07-09 12:14:50 +02:00
ccbf141850
compiler-rt: update to new location, fixes #209
2019-07-08 23:03:23 +02:00
21a5aaa4a6
soc_core: declare csr address size when registering csr, fixes #212
2019-07-08 22:58:07 +02:00
41b6fbde42
soc_cores: fix typos
2019-07-08 22:56:14 +02:00
bff081a818
Merge pull request #214 from gsomlo/gls-alignment-fixup
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soc_core: additional csr_alignment follow-up fixes
2019-07-08 19:03:28 +02:00
e42f33ede1
soc_core: additional csr_alignment follow-up fixes
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- Update a few additional places to use DFII_ADDR_SHIFT instead of
a hard-coded 4, which assumed 32-bit alignment.
- Force 64-bit alignment Rocket -- the only supported configuration!
This is a fixup for commit f4770219
2019-07-08 10:15:14 -04:00
f4770219fa
soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs
2019-07-08 10:20:51 +02:00
927b7c13a2
soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant)
2019-07-08 08:57:05 +02:00
Mateusz Holenko
Florent Kermarrec
Francis Lam
chmousset
Ilia Sergachev
Gabriel L. Somlo