Commit Graph

3590 Commits

Author SHA1 Message Date
Florent Kermarrec d85d2b7b9b soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field 2015-11-27 20:14:01 +01:00
Florent Kermarrec c0539fff3e boards: add new digilent arty 2015-11-27 00:29:30 +01:00
Florent Kermarrec c24727ab4c soc/integration: allow using builder with soc.cpu_type == None 2015-11-26 17:44:50 +01:00
Florent Kermarrec 7298fff1e6 soc/interconnect/stream_packet: fix Counter removing 2015-11-24 20:30:53 +01:00
Florent Kermarrec 8ebffc563a soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister 2015-11-23 19:13:37 +01:00
Florent Kermarrec 254504e73f soc/integration/builder: export constants and memory_regions with csr_csv 2015-11-23 19:12:58 +01:00
Florent Kermarrec f6a2d5847a soc/tools/remote/client: make csr_csv parameter optional and default value to None 2015-11-23 18:39:28 +01:00
Florent Kermarrec 6f4dd14ffa soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant 2015-11-23 11:08:04 +01:00
Florent Kermarrec cb22a207f1 build/generic_platform: add support for int parameter for Pins (useful for core generation) 2015-11-19 14:57:09 +01:00
Florent Kermarrec 8056653004 soc/tools/remote/server: add --debug parameter 2015-11-17 15:43:10 +01:00
Florent Kermarrec 6870707620 soc/tools/remoter/server: fix exit on KeyboardInterrupt 2015-11-17 15:31:23 +01:00
Florent Kermarrec 8ff31557c6 soc/tools/remoter/server: add some printfs 2015-11-17 15:18:46 +01:00
Florent Kermarrec 1a92489555 soc/tools/remote: add comm_pcie and comm_udp (to be tested) 2015-11-17 15:07:00 +01:00
Florent Kermarrec d6fdd76930 soc/tools/remote: small cleanup and remove csr_data_width from server side 2015-11-17 11:35:22 +01:00
Florent Kermarrec 71483b8935 soc/tools: initialize wishbone remote control (for now only uart) 2015-11-17 01:05:52 +01:00
Florent Kermarrec 1cde84dccf soc/cores/uart remove software (will be re-written and will move to soc/tools) 2015-11-16 17:07:22 +01:00
Florent Kermarrec 1f80bb9561 soc/interconnect/stream_packet: remove Counter 2015-11-16 16:53:23 +01:00
Florent Kermarrec ec35290c45 soc/interconnect/wishbonebridge: remove Counter 2015-11-16 16:48:37 +01:00
Florent Kermarrec 6fd0b73817 build: remove edif support 2015-11-16 16:26:38 +01:00
Florent Kermarrec e407a1cdda gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign 2015-11-16 16:18:09 +01:00
Florent Kermarrec 2f52d364af soc/interconnect/stream/SyncFIFO: expose fifo level 2015-11-16 16:11:31 +01:00
Florent Kermarrec 7ed2576ce1 soc/integration/cpu_interface: add bases, constants and memories output to csv files 2015-11-15 00:04:44 +01:00
Florent Kermarrec af909b43d5 soc/cores/uart: add UARTWishboneBridgeDriver software 2015-11-14 21:23:20 +01:00
Florent Kermarrec 3a2e6117f4 soc/interconnect/stream: add Cast and others small fixes 2015-11-14 12:17:09 +01:00
Florent Kermarrec 041483dbe1 soc/integration/builder: only copy Makefiles when not using symlinks 2015-11-14 03:36:46 +01:00
Florent Kermarrec a2aa5726bf soc/cores: remove liteeth_mini and use liteeth 2015-11-14 03:22:43 +01:00
Florent Kermarrec 16ba646b1b add TODOs 2015-11-14 03:15:10 +01:00
Florent Kermarrec cf4c7da2e7 fix soc/integration/soc_core.py 2015-11-14 02:44:12 +01:00
Florent Kermarrec 032f5a9620 soc/interconnect: add stream_sim 2015-11-14 00:43:49 +01:00
Florent Kermarrec ba959c832d soc/interconnect: rename packet to stream_packet 2015-11-14 00:42:58 +01:00
Florent Kermarrec 1158b98fdd doc: update logo 2015-11-13 23:40:27 +01:00
Florent Kermarrec fc3ffe87ac for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
Florent Kermarrec ae3d54499a litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented 2015-11-13 14:44:16 +01:00
Florent Kermarrec 7d6cee6751 soc/interconnect/stream: add BufferizeEndpoints 2015-11-12 18:54:15 +01:00
Florent Kermarrec 83427c87cd soc/interconnect/stream: add Pipeline 2015-11-12 01:41:23 +01:00
Florent Kermarrec 81c6facca2 soc/interconnect/stream: reintroduce params 2015-11-12 01:12:15 +01:00
Florent Kermarrec f6b30fcae2 soc/interconnect: add packet 2015-11-12 00:54:40 +01:00
Florent Kermarrec 525da89c7d soc/interconnect: add wishbonebridge and uart bridge 2015-11-12 00:52:36 +01:00
Florent Kermarrec 89b189ce4a soc/interconnect/stream: reintroduce PipelinedActor/Buffer 2015-11-12 00:51:32 +01:00
Florent Kermarrec 194e6137ae soc/integration/soc_core: add support for SoCs without CPU 2015-11-12 00:50:23 +01:00
Florent Kermarrec 57c0f85656 README: update 2015-11-11 17:38:12 +01:00
Florent Kermarrec c076c2cbd6 boards/targets: remove papilio_pro/pipistrello 2015-11-11 17:38:03 +01:00
Florent Kermarrec 352cb91688 soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
2015-11-11 17:37:28 +01:00
Florent Kermarrec 1cec0f8086 boards/targets/sim: add ethernet support 2015-11-11 14:23:39 +01:00
Florent Kermarrec 1f6983da2c soc/cores/liteeth_mini: add phy model for verilator simulation 2015-11-11 14:22:27 +01:00
Florent Kermarrec 481163b233 soc/cores: reintroduce liteeth_mini (until we switch to liteeth) 2015-11-11 14:01:48 +01:00
Florent Kermarrec d0ec57add6 doc: add logo 2015-11-11 13:36:29 +01:00
Florent Kermarrec 714a3d88e2 add LICENSE, update copyrights, add Migen install instructions 2015-11-11 13:22:39 +01:00
Florent Kermarrec bda196fbc8 soc/software/bios/sdram: split memtest and allow external #define of memtest sizes 2015-11-11 13:10:03 +01:00
Florent Kermarrec 619cd8e695 avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules 2015-11-11 12:10:55 +01:00