enjoy-digital
14b2829a5f
Merge pull request #1467 from enjoy-digital/csr_mapping
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Add optional support for fixed CSR mapping.
2022-10-21 18:36:26 +02:00
Florent Kermarrec
a60a51c52f
interconnect/csr: Only sort gathered items at Module level.
2022-10-21 16:04:23 +02:00
Florent Kermarrec
a57f0640cc
soc/interconnect/csr: Add optional support fixed CSR mapping.
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By default, location is still automatically determined but it's now possible to
specific locations:
The following module:
class MyModule(Module, AutoCSR):
def __init__(self):
self.csr0 = CSRStorage()
self.csr1 = CSRStorage(n=0)
self.csr2 = CSRStorage(n=2)
built on a SoC with 32-bit CSR data-width will have the following CSR mapping:
- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2
2022-10-21 14:47:59 +02:00
Florent Kermarrec
804a1a5b26
soc/add_uart: Improve error message for unsupported UART.
2022-10-21 09:03:25 +02:00
Florent Kermarrec
73d70cf594
build/sim/platform: Remove add_csr calls no longer required.
2022-10-21 08:43:51 +02:00
enjoy-digital
525bbd19a9
Merge pull request #1465 from mohamedElbouazzati/cv32e41p_interrupts
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Fix IRQS handling for cv32e41p
2022-10-20 16:00:39 +02:00
mohamedElbouazzati
85e9881f45
Fix IRQS for cv32e41p
2022-10-19 17:48:36 +02:00
Florent Kermarrec
da8d3d10aa
tools/litex_read_verilog: Add proc step before exporting to .json since now seems to be required for some verilog designs.
2022-10-19 15:29:00 +02:00
Florent Kermarrec
89670e5938
soc/cores/spi: Add SPIBone import.
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Allow importing SPIBone with:
from litex.soc.cores.spi import SPIBone
2022-10-19 15:22:04 +02:00
Florent Kermarrec
519b411954
core/spi/spi_bone: Update header.
2022-10-19 11:40:51 +02:00
Florent Kermarrec
4e8e97a22a
cores/spi/spi_bone: Cosmetic cleanups on FSM (rename states).
2022-10-19 11:40:23 +02:00
Florent Kermarrec
bdfb032be9
cores/spi/spi_bone: More cosmetic cleanups.
2022-10-19 11:29:03 +02:00
Florent Kermarrec
0b05abb44f
cores/spi/spi_bone: Rename self.wishbone to self.bus/bus.
2022-10-19 11:10:21 +02:00
Florent Kermarrec
b6b3ab4f11
cores/spi/spi_bone: Move Clk edges detection and rename signals (rising -> posedge, falling -> negedge).
2022-10-19 11:02:43 +02:00
Florent Kermarrec
710a1958a4
cores/spi/spi_bone: Separate SPI IOs handling from Signals.
2022-10-19 10:55:44 +02:00
Florent Kermarrec
2a15ab554a
cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases.
2022-10-19 10:53:26 +02:00
Florent Kermarrec
eabdc0b7e9
cores/spi/spi_bone: Cosmetic cleanup pass (and remove unreachable ValueErrors).
2022-10-19 10:48:13 +02:00
Florent Kermarrec
296fc7add0
cores/spi/spi_bone: Spi -> SPI and rename SpiWishboneBridge to SPIBone.
2022-10-19 10:37:11 +02:00
Florent Kermarrec
b6069a4d62
soc/cores/spi/spi_master: Remove SPISlave.
2022-10-18 18:22:33 +02:00
Sean Cross
9f52ed1207
soc/cores/spi: Integrate SPIWishboneBridge from https://github.com/xobs/spibone .
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"The ability to bridge Wishbone is an incredibly powerful one. However, the various bridges can be rather heavy in terms of resource usage. This presents a simple bridge that operates over SPI."
2022-10-18 18:20:50 +02:00
Florent Kermarrec
f5c9425e14
soc/cores/spi: Create spi directory and split spi.py in spi_master/spi_slave.
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__init__.py provide imports compatibility.
2022-10-18 18:16:35 +02:00
Florent Kermarrec
f7e05b1953
interconnect/axi: Add 8-bit/16-bit data-widths.
2022-10-18 14:15:08 +02:00
Florent Kermarrec
838a30f148
interconnect/stream/Monitor: Add reset/latch control from logic.
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Useful when multiple Monitors modules needs to be reseted/latched synchronously from user logic.
2022-10-18 09:21:00 +02:00
Florent Kermarrec
7bd0311947
interconnect/stream/Monitor: Fix packet support and cleanup.
2022-10-17 18:42:34 +02:00
Florent Kermarrec
b990b90c0e
soc/interconnect/stream/Monitor: Add Packets count (with configurable delimiter: first or last).
2022-10-14 20:04:48 +02:00
Florent Kermarrec
a03013e427
ci: Bump to ubuntu 20.04.
2022-10-14 18:21:19 +02:00
Florent Kermarrec
24cfbd8d67
build/efinity: Update to 2022.1.226.
2022-10-14 10:25:44 +02:00
Florent Kermarrec
84db6a0b3a
interconnect/axi: Add AXI version to AXIInterface (default to AXI4) and handle AXI3/AXI4 differences.
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- Max burst length of 16 in AXI3, 256 in AXI4.
- No WID in AXI4.
2022-10-13 11:04:00 +02:00
Florent Kermarrec
a8070051b5
cpu/microwatt: Switch to VHD2VConverter to simplify code.
2022-10-13 09:23:20 +02:00
Florent Kermarrec
3e23ad3cff
build/vhd2v_converter: Fix add_sources (to make it similar to platform.add_sources).
2022-10-13 09:12:58 +02:00
enjoy-digital
808cf1a466
Merge pull request #1460 from enjoy-digital/neorv32_params
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cpu/neorv32/core: Avoid configure_litex_core_complex by passing param…
2022-10-12 21:18:14 +02:00
Florent Kermarrec
74ae18ddaa
cpu/neorv32/core: Avoid configure_litex_core_complex by passing params to new VHD2VConverter.
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Parameters are passed to Yosys to configure them at the top level before VHDL->Verilog conversion.
2022-10-12 14:47:28 +02:00
Florent Kermarrec
efdc9ecef9
build/vhd2v_converter: Always do params -> constants translation.
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Useful when instance is done in the code but params are just passed to VHD2VConverter.
2022-10-12 14:35:43 +02:00
Florent Kermarrec
03a5f16d70
build/vhd2v_converter: Add list of things to check.
2022-10-12 12:07:41 +02:00
Florent Kermarrec
00f29a3497
build: Rename VHDLWrapper to VHD2VConverter (more explicit).
2022-10-12 11:57:27 +02:00
Florent Kermarrec
848245bf59
build/sim/verilator: Add missing support_mixed_language property.
2022-10-12 11:49:42 +02:00
enjoy-digital
c700f9d0ef
Merge pull request #1453 from trabucayre/vhdl_wrapper
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Vhdl wrapper
2022-10-12 11:42:51 +02:00
enjoy-digital
bf1349bd17
Merge pull request #1458 from antmicro/rowhammer-etherbone-retry
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Added retransmission logic for EtherBone UDP reads.
2022-10-12 11:27:43 +02:00
Florent Kermarrec
ac3699770c
interconnect/stream/ClockDomainCrossing: Expose buffered parameter.
2022-10-06 18:30:02 +02:00
enjoy-digital
75bf668883
Merge pull request #1450 from tpwrules/improve-intel-pll-calculation
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soc/cores/clock: improve Intel PLL calculation
2022-10-06 12:06:58 +02:00
enjoy-digital
b47ebf2ce7
Merge pull request #1449 from tpwrules/fix-quartus-clock-constraints
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build/altera: fix clock constraints
2022-10-06 11:59:31 +02:00
Gwenhael Goavec-Merou
536e24f715
soc/cores/cpu/neorv32: convert to VHDLWrapper
2022-10-05 14:10:45 +02:00
Gwenhael Goavec-Merou
8eef2cda0d
build/VHDLWrapper: adding a class to factorize VHDL handling
2022-10-05 14:09:06 +02:00
Florent Kermarrec
aa17c27eb9
interconnect/axi/axi_stream: Add clock_domain parameters.
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Useful for wrapping IP and do checks or decide if CDC has to be inserted.
2022-10-05 11:07:34 +02:00
Thomas Watson
fea73d932e
soc/cores/clock/intel: speed up PLL config computation
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Caching the list of clock divisors to test speeds up computation by
about a factor of three.
2022-10-01 13:08:16 -05:00
Thomas Watson
b7ef989963
soc/cores/clock/intel_*: respect PFD input frequency
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Only use input clock divisors which respect the device limitation for
the phase-frequency detector's input frequency. This avoids errors where
Quartus complains the PLL parameters are invalid and refuses to
implement it.
The supported PFD frequencies in integer mode have been verified against
each family's datasheet. The unsupported-by-LiteX fractional frequency
information is removed for clarity.
As a bonus, this speeds up PLL config computation by several times.
2022-10-01 13:00:24 -05:00
Thomas Watson
d89d6dfd0a
soc/cores/clock/intel_common: cleanup
2022-10-01 12:28:32 -05:00
Thomas Watson
d531a07719
build/altera: fix clock constraints
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This fixes two issues that prevented clock constraints (e.g.
"add_false_path_constraint") from working properly in Quartus.
The first fix passes the "keep" synthesis attribute through to the
generated Verilog in a way Quartus can understand.
The second fix tells Quartus to name PLL clocks according to their net
instead of the physical pin name by passing the "use_net_name" flag to
"derive_pll_clocks" in the .sdc file. Combined with the above, PLL
clocks will now be named according to the kept net.
This fix has been verified on Quartus Prime Lite 20.1.1.720.
2022-09-30 23:33:52 -05:00
Thomas Watson
d27d6fca62
soc/cores/video: fix framebuffer color output
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An earlier patch fixed the swapped red and blue channels on the HDMI
PHYs. This exposed the fact that the framebuffer readout was swapped
too.
The framebuffer readout is fixed by this patch to match the r5g6b5 and
a8b8g8r8 color format definitions documented in the Linux kernel's
simplefb driver and used by LiteX:
https://www.kernel.org/doc/Documentation/devicetree/bindings/display/simple-framebuffer.txt
This has been tested using 16 bit SDRAM in both supported color formats.
Additionally the green color used by the video terminal is swapped. It
now matches the color used by LiteX on Ubuntu's terminal, from which it
was probably originally sourced.
2022-09-30 19:15:56 -05:00
Dolu1990
3836e8a36c
Merge pull request #1447 from enjoy-digital/naxriscv-merge
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cpu/naxriscv reduce memory latency on peripheral accesses
2022-09-30 16:21:23 +02:00