8e639160e3
liteeth/phy/gmii_mii: add pads registers in RX
2015-04-12 20:43:01 +02:00
0c27708b0a
liteeth/phy/gmii_mii: avoid doubling pads register on TX
2015-04-12 20:42:12 +02:00
bc81d9d639
liteeth/phy/__init__.py: add more comments
2015-04-12 18:56:46 +02:00
4abe8e1d9e
microudp: fix if (
2015-04-12 18:52:35 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
857bee8a00
liteeth/phy: add GMII/MII phy
...
for now swicth is manual, we will need a clk counter to allow software or logic to automatically switch between GMII and MII
2015-04-12 17:25:55 +02:00
cfac3d9f5c
liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter
2015-04-12 16:03:21 +02:00
ddae41f2e4
liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
2015-04-12 15:34:56 +02:00
8c722db54e
liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII)
2015-04-12 14:43:35 +02:00
4329e3e1b9
liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)
2015-04-12 14:28:17 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
93ed3212f7
timer: revert prescaler (we will in fact use a software prescaler for uIP)
2015-04-10 18:57:06 +02:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
80ef7291c1
timer: add prescaler
2015-04-10 13:58:44 +02:00
181aeb4791
Add example of hamming generator and checker instances
...
--089e01294e809a874205133faa19
Content-Type: text/plain; charset=UTF-8
<div dir="ltr"><br></div>
2015-04-10 16:15:55 +08:00
d6c19858fa
s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
2015-04-10 16:12:29 +08:00
603a4ef51e
liteeth: adapt to new ModuleTransformer
2015-04-10 11:42:25 +08:00
5d07072783
strace_tailor: make more generic, cleanup
2015-04-10 11:07:16 +08:00
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
ea613cd8ee
litesata: update build core target generation
2015-04-09 00:00:25 +02:00
03aa972bb6
lite*: finish ModuleTransformer adaptations (need to be tested on board)
2015-04-08 23:27:22 +02:00
3a2b677f85
soc,cpuif: support user defined constants
2015-04-09 00:34:36 +08:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
8ce683964a
mibuild/tools/write_to_file: use context manager
2015-04-08 19:41:54 +08:00
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
8b41ab3a5f
make: add target in build names
2015-04-06 23:53:04 +08:00
176b9240a9
soc: use new ModuleTransformer API
2015-04-06 23:52:34 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
66f8dcbfaf
lite*: adapt to new ModuleTransformer semantics
...
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
aac953dd90
vivado: support phys_opt
2015-04-04 19:00:22 +08:00
9506f69390
vivado: add support for pre_synthesis_commands
2015-04-04 19:00:01 +08:00
4522956f11
vivado: make _build_files() a method and rename
2015-04-04 18:59:50 +08:00
1d1189506a
mibuild: support multiple specifications of include file and sources
2015-04-04 18:58:02 +08:00
2583e975f0
soc/cpuif: fix CSR base generation for memories (name is already fullname)
2015-04-03 13:57:37 +02:00
c9c11e7aa8
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
2015-04-03 12:45:32 +02:00
85b3cced22
use str.format
2015-04-03 17:43:46 +08:00
c7361f1cdf
software/common.mak: fix alignment in quiet output
2015-04-03 17:43:29 +08:00
0db6e1d624
soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
2015-04-03 11:14:28 +02:00
875abdeb8d
make.py: use os.path.join
2015-04-03 16:00:07 +08:00
73d3b8487c
crt0-or1k: clean up indentation
2015-04-03 13:23:28 +08:00
357c807eb1
Merge branch 'master' of github.com:m-labs/migen
2015-04-02 20:23:12 +08:00
ce429841d5
kc705: fix typo in platform file (LPC definition)
2015-04-02 20:21:20 +08:00
b437dc3185
remove use of _r prefix on CSRs
2015-04-02 12:18:43 +02:00
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
d67f24ddc7
migen/bank/description: remove support of _r prefix in CSRs
2015-04-02 12:13:22 +02:00
Florent Kermarrec
Sebastien Bourdeauducq
Guy Hutchison
Robert Jordens
Yann Sionneau