Florent Kermarrec
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24211574ec
|
update de0nano example/ remove de1 (wip)
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2013-03-18 23:03:52 +01:00 |
|
Florent Kermarrec
|
36f3556028
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Add uart2csr
|
2013-03-18 21:45:07 +01:00 |
Sebastien Bourdeauducq
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28cb97068c
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dvisampler/clocking: proper pix5x reset synchronization
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2013-03-18 20:31:59 +01:00 |
|
Sebastien Bourdeauducq
|
5126f616fb
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dvisampler: use pix5x as IODELAY clock
|
2013-03-18 19:03:17 +01:00 |
|
Sebastien Bourdeauducq
|
48aae9bee5
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Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
|
2013-03-18 17:44:01 +01:00 |
|
Sebastien Bourdeauducq
|
0c0140a8fb
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m1crg: set CLKIN_PERIOD for vga_clock_gen
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2013-03-17 20:16:58 +01:00 |
|
Sebastien Bourdeauducq
|
74cc045ee1
|
dvisampler/datacapture: connect IODELAY IOCLK0
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2013-03-17 17:42:22 +01:00 |
|
Sebastien Bourdeauducq
|
621526fb7d
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dvisampler/datacapture: fix tap counter reg
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2013-03-17 17:36:49 +01:00 |
|
Sebastien Bourdeauducq
|
3a0cf278fd
|
dvisampler: fixes
|
2013-03-17 15:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
9f02ced39e
|
dvisampler: add clocking and phase detector
|
2013-03-17 14:43:10 +01:00 |
|
Sebastien Bourdeauducq
|
0168f83523
|
MultiReg: remove idomain
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2013-03-15 19:51:29 +01:00 |
|
Sebastien Bourdeauducq
|
b2173bba9f
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Use new ClockDomain API
|
2013-03-15 19:17:05 +01:00 |
|
Sebastien Bourdeauducq
|
2ae504fb9b
|
software/bios: default length 4 for mr command
|
2013-03-13 19:59:39 +01:00 |
|
Sebastien Bourdeauducq
|
eaef3464e9
|
Instantiate DVI sampler core for both ports
|
2013-03-13 19:56:56 +01:00 |
|
Sebastien Bourdeauducq
|
e99bafe52b
|
dvisampler: add core, EDID support
|
2013-03-13 19:56:26 +01:00 |
|
Sebastien Bourdeauducq
|
1e7783a41e
|
build.py: use implicit get_fragment
|
2013-03-12 16:13:20 +01:00 |
|
Sebastien Bourdeauducq
|
a23df42a7a
|
Use automatic register naming
|
2013-03-12 15:47:54 +01:00 |
|
Florent Kermarrec
|
60e2cdfe79
|
get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection
|
2013-03-11 20:05:30 +01:00 |
|
Sebastien Bourdeauducq
|
a9b723568a
|
Use new module, autoreg and eventmanager Migen APIs
|
2013-03-10 19:32:38 +01:00 |
|
Sebastien Bourdeauducq
|
2059592db2
|
software/libcompiler-rt: add ctzsi2
|
2013-03-06 11:10:16 +01:00 |
|
Florent Kermarrec
|
edce543b14
|
adapt to migen changes
|
2013-03-01 01:09:00 +01:00 |
|
Florent Kermarrec
|
80e9db7e61
|
use mibuild for de1 example
|
2013-02-28 23:11:41 +01:00 |
|
Florent Kermarrec
|
58a6acba27
|
use mibuild for de0_nano example
|
2013-02-28 23:02:06 +01:00 |
|
Florent Kermarrec
|
58edd7632c
|
compiles but untested
|
2013-02-28 00:32:42 +01:00 |
|
Florent Kermarrec
|
5accd48a17
|
doc: update
|
2013-02-26 23:45:01 +01:00 |
|
Florent Kermarrec
|
87336128a3
|
sim: update
|
2013-02-26 23:25:10 +01:00 |
|
Florent Kermarrec
|
ae900c9c16
|
examples: use miscope.bridges
|
2013-02-26 23:20:29 +01:00 |
|
Florent Kermarrec
|
5fc89f0c71
|
move spi2csr to briges/spi2csr
|
2013-02-26 23:17:34 +01:00 |
|
Florent Kermarrec
|
f823d06cf1
|
examples: update & simplify
|
2013-02-26 23:14:09 +01:00 |
|
Florent Kermarrec
|
b3ae31ee2f
|
examples/../top: update
|
2013-02-26 23:00:37 +01:00 |
|
Sebastien Bourdeauducq
|
356416fcdc
|
lm32: update
|
2013-02-24 17:42:28 +01:00 |
|
Sebastien Bourdeauducq
|
70f4c74d46
|
m1crg: advance off-chip DDR clock phase
|
2013-02-24 17:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
5e6505b946
|
bios: print number of memory errors
|
2013-02-24 16:51:03 +01:00 |
|
Sebastien Bourdeauducq
|
b854f1ad32
|
build: support optional MMU
|
2013-02-24 16:28:59 +01:00 |
|
Sebastien Bourdeauducq
|
43343b131f
|
lm32: use submodule
|
2013-02-24 15:57:19 +01:00 |
|
Sebastien Bourdeauducq
|
0caac2246d
|
Use new 'specials' API
|
2013-02-24 13:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
a22ada36d7
|
corelogic -> genlib
|
2013-02-24 12:31:00 +01:00 |
|
Florent Kermarrec
|
e95e8b03b7
|
- reworking WIP
|
2013-02-22 16:40:49 +01:00 |
|
Sebastien Bourdeauducq
|
dfec152422
|
Build FPG file
|
2013-02-19 13:27:43 +01:00 |
|
Sebastien Bourdeauducq
|
3f22930b1f
|
tools: add byteswap
|
2013-02-19 13:22:35 +01:00 |
|
Sebastien Bourdeauducq
|
07120e3c3e
|
bios: use puts for long string
|
2013-02-17 16:21:25 +01:00 |
|
Sebastien Bourdeauducq
|
8247f3a154
|
bios: add build date to banner
|
2013-02-17 14:29:11 +01:00 |
|
Sebastien Bourdeauducq
|
b135d87ca2
|
Makefile: correct bitstream filename
|
2013-02-17 00:12:15 +01:00 |
|
Sebastien Bourdeauducq
|
20003f0ada
|
software: go back to GCC
|
2013-02-16 23:41:42 +01:00 |
|
Sebastien Bourdeauducq
|
c56c916129
|
load.jtag: remove CFG_OUT/CFG_IN instructions
|
2013-02-15 19:39:54 +01:00 |
|
Sebastien Bourdeauducq
|
7ad2f7081b
|
m1crg: fix signal names
|
2013-02-13 23:59:35 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
f68fcef90c
|
tb: use default runner
|
2013-02-09 17:09:29 +01:00 |
|
Florent Kermarrec
|
21b6772448
|
- fix timings.py
|
2013-01-27 13:59:44 +01:00 |
|
Florent Kermarrec
|
8975fa2e44
|
- update README...
|
2013-01-21 22:40:36 +01:00 |