f224036138
stream/ClockDomainCrossing: Revert with_common_rst to False by default (Previous behavior).
...
This seems to cause issues in simulation on some cores, this will first have to be fixed before
using it as default. Cores requiring it will set it to True explicitly for now.
2022-04-05 19:53:00 +02:00
ed6a6a83a9
litex_setup: Switch to manual install for Amaranth/Minerva (No longer supporting Python 3.6).
...
We could revert when upgrading LiteX python requirement.
2022-04-04 15:39:05 +02:00
d39c3ed626
soc/cores/led: Review/Rework #1265 .
...
- Split FSM in Main FSM/Xfer FSM to decouple Led data read from bit xfer and do read during xfer.
- Only keep optimization that are easily to understand.
- Default to new WS2812 revision (Since also works on old revision).
- Test 75/50/25MHz sys_clk_freq.
2022-04-04 15:24:54 +02:00
bd6f5fbf9d
Merge pull request #1265 from wnagele/ws2812_improvements
...
Improve WS2812 timings and add different hardware revision support
2022-04-04 15:20:15 +02:00
df1cb4eea1
Merge pull request #1262 from developandplay/demo-fix-bp
...
Fix demo.bin compilation for BlackParrot
2022-04-04 08:42:08 +02:00
67369403a9
Improve WS2812 timings and add different hardware revision support
2022-04-03 17:09:56 +02:00
1106da4e35
Fix demo bin compilation for BlackParrot
...
Same issue as:
https://github.com/enjoy-digital/litex/pull/1245
2022-04-02 00:18:39 +02:00
c400479174
stream/ClockDomainCrossing: Add Python's ID to local clock domain names to fix build with anonymous modules.
2022-04-01 15:56:49 +02:00
80b309d1a4
Merge pull request #1258 from antmicro/4_bit_dqs
...
Make memtest work with 4x DQ / DQS ratio
2022-03-31 17:21:07 +02:00
f49d2953ed
Make memtest work with 4x DQ / DQS ratio
2022-03-30 13:46:48 +02:00
aa3506a393
build/sim/common: Add SimAsyncResetSynchronizerImpl.
2022-03-29 19:09:54 +02:00
f944b656d5
stream/ClockDomainCrossing: Make common reset an option (Enabled by default).
2022-03-29 17:07:20 +02:00
38a7b1fee0
stream/ClockDomainCrossing: Reset both clock domains through an AsyncResetSynchronizer when one of the two clock domains is reseted.
2022-03-29 16:41:20 +02:00
9be3951be9
Merge pull request #1256 from fjullien/mipi_rx
...
efinix: add MIPI RX controller in ifacewriter
2022-03-29 14:31:05 +02:00
5542837965
efinix: add MIPI RX controller in ifacewriter
2022-03-29 12:07:20 +02:00
d117edc81c
CHANGES: Update.
2022-03-29 11:35:27 +02:00
e8ed297763
cpu/vexriscv_smp: Fix pbus width when using direct LiteDRAM interface (always 32-bit).
2022-03-28 16:03:14 +02:00
d214c37b76
build/efinix/programmer: Minor import changes and upadte copyrights.
2022-03-28 14:56:35 +02:00
ba6d9f0751
Merge pull request #1254 from chmousset/add_efinix_usb_loader
...
[enh] added efinix atmel programmer
2022-03-28 14:54:13 +02:00
6e62ac1818
[enh] added efinix atmel programmer
2022-03-26 09:40:28 +01:00
a0853d15ca
Merge pull request #1251 from motec-research/field_size
...
export: fix mask for field size 31
2022-03-25 09:35:51 +01:00
d9e39d64b3
export: fix mask for field size 31
...
software/include/generated/csr.h:110:2: warning: integer overflow in expression '-2147483648 - 1' of type 'int' results in '2147483647' [-Woverflow]
uint32_t mask = ((1 << 31)-1);
^~~~~~~~
2022-03-25 09:19:16 +11:00
0bd2abf68d
Merge pull request #1250 from pftbest/connect_to_pads_last
...
Fix missing "last" pin connection when using connect_to_pads
2022-03-24 14:46:25 +01:00
967ea12364
cpu/vexriscv_smp: Fix pbus data-width (Max of icache/dcache-width).
...
Fix boot with > 1 CPU or with FPU when using --with-wishbone-memory.
2022-03-24 14:34:38 +01:00
0ac3d677b5
bios/main: Test Main RAM only when not pre-initialized (corrupt contents otherwise).
2022-03-24 14:34:29 +01:00
d3f3f658cb
integration/soc: Generate RAM_INIT config defined when ram is initialized.
2022-03-24 14:34:26 +01:00
c1898b9355
Fix missing "last" pin connection when using connect_to_pads
...
When using connect_to_pads on full AXI interface the "last" pin was not connected because of this typo.
2022-03-24 15:37:59 +04:00
ef6d450820
Merge pull request #1249 from enjoy-digital/setup_fix
...
Fix litex_setup.py and use local version on CI.
2022-03-24 10:59:44 +01:00
caced992ad
litex_setup: Remove pip3 install amaranth-yosys.
2022-03-24 10:33:10 +01:00
1935a2599f
workflows/ci: Use local version of litex_setup.
2022-03-24 10:17:08 +01:00
72b61155c7
workflows/ci: Checkout to /usr/litex.
2022-03-24 10:12:38 +01:00
41bd8539c3
setup.py: Remove migen/pythondata-software-compiler-rt (Installed through litex_setup.py).
2022-03-24 10:06:31 +01:00
a3b62c9b95
Merge pull request #1248 from motec-research/pip_install
...
litex_setup: change to installing with pip
2022-03-24 09:53:17 +01:00
3f72cd30b1
litex_setup: change to installing with pip
...
fixes: EasyInstallDeprecationWarning: easy_install command is deprecated. Use build and pip and other standards-based tools.
2022-03-23 11:22:56 +11:00
dd7a04a5c0
liblitedram/sdram_leveling_center_module: Do a check after final delay configuration.
...
On ECP5/DDR3, final configuration does not seem to be done correctly each time.
Add a retry/check mechanism to workaround the issue for now.
2022-03-22 17:12:50 +01:00
153f9f3660
soc_core: Fix l2_size argument handling.
2022-03-22 11:23:01 +01:00
f0bd7019cd
soc/add_jtagbone/add_sdram: Add/Use name parameter.
2022-03-22 09:53:48 +01:00
e227f3b038
soc: Improve logs on add_controller, add_csr_bridge and add_cpu.
2022-03-22 09:41:20 +01:00
33d6c3de8f
builder/soc_core: Add missing title.
2022-03-21 18:07:34 +01:00
901428f5a9
soc/add_ethernet: Fix add_ethernet.
2022-03-21 18:03:40 +01:00
be23a059ff
soc/interconnect/csr/CSRConstant: Add constant attribute.
2022-03-21 18:03:15 +01:00
4a5ce77d40
build/soc/cpu parser: Improve titles.
2022-03-21 17:53:30 +01:00
1e6e9777e2
Merge pull request #1245 from developandplay/demo-fix
...
Fix compilation of demo.bin on Rocket
2022-03-21 17:15:59 +01:00
1583cc8a40
cpu/naxriscv: Add default value to xlen argument.
2022-03-21 17:14:24 +01:00
8e440dc9ea
soc/integration: Add LiteXSocArgumentParser to be able to expose CPU parameters to user on targets.
...
Currently used for CPU parameters could problably be extented to simplify other parts
of the code in the future.
2022-03-21 16:57:14 +01:00
6ef96b17bc
soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
2022-03-21 15:21:08 +01:00
f5d4977dde
Merge pull request #1246 from gsomlo/gls-memtest-cast-warning
...
bios/memtest: fix cast warning
2022-03-20 21:09:36 +01:00
e5a2305269
bios/memtest: fix cast warning
2022-03-20 14:30:16 -04:00
884ee45c28
Fix compilation of demo.bin on Rocket
...
- Adjust memory model to fix `relocation truncated` errors
- Make isr.c shared between BIOS and demo to resolve dep on `plic_init`
Based on: https://github.com/enjoy-digital/litex/issues/1168
2022-03-20 15:39:13 +01:00
f565bec7f1
cpu/naxriscv fix xlen not being hashed, improve RV64 performances
2022-03-18 15:39:58 +01:00
Florent Kermarrec
Wolfgang Nagele
developandplay
Piotr Binkowski
Franck Jullien
Charles-Henri Mousset
Andrew Dennison
Vadzim Dambrouski
Dolu1990
Gabriel Somlo