Commit Graph

165 Commits

Author SHA1 Message Date
Florent Kermarrec 2f6465d439 add sigrok import (to check export against it) 2015-02-18 15:23:04 +01:00
Florent Kermarrec 130212039e continue sigrok export (should almost work) 2015-02-18 11:59:35 +01:00
Florent Kermarrec cd43163d9d add sigrok export skeleton (wip) 2015-02-18 00:44:33 +01:00
Florent Kermarrec 5830575797 logo : add powered by Migen 2015-02-17 23:14:21 +01:00
Florent Kermarrec a5416fa864 host: add Etherbone driver 2015-02-17 01:09:53 +01:00
Florent Kermarrec b64dba7a81 update download instructions 2015-02-12 22:03:04 +01:00
Florent Kermarrec 04f7fbd7e2 simplify litescope export with do_exit call and remove automatic clean 2015-02-12 21:15:51 +01:00
Florent Kermarrec 989cca24bc uart2wb: copy UARTTX/UARTRX from MiSoC to avoid dependency 2015-02-02 14:23:01 +01:00
Florent Kermarrec f65848ca92 doc : add link to generated html/pdf 2015-01-28 19:59:49 +01:00
Florent Kermarrec 615d7da703 README: fix tabs 2015-01-28 15:55:52 +01:00
Florent Kermarrec 9d6a3e7f2a doc: add skeleton 2015-01-27 21:35:58 +01:00
Florent Kermarrec 0c907e5afa fill building parameters 2015-01-27 20:24:14 +01:00
Florent Kermarrec 7f9174f83d add storage qualifier 2015-01-27 20:14:07 +01:00
Florent Kermarrec fc96b20225 add optional subsampler 2015-01-27 19:58:02 +01:00
Florent Kermarrec 70d7152cda core/storage: split LiteScopeRecorder in LiteScopeRecorderUnit and LiteScopeRecorder 2015-01-27 11:34:59 +01:00
Florent Kermarrec 64d18796e0 change CSR class names (do not expose XXYYCSR to user) 2015-01-25 21:34:13 +01:00
Florent Kermarrec a3dae5fc5c host/driver: simplify 2015-01-25 16:13:06 +01:00
Florent Kermarrec 4472dac603 simplify code and use Sink/Source instead of records 2015-01-25 15:58:00 +01:00
Florent Kermarrec 6f7d85b95c host: remove cpuif (we use the one from MiSoC) and some clean up 2015-01-23 16:45:04 +01:00
Florent Kermarrec 9a3e9f86cf simplify LiteScopeLA export (use vns from platform on atexit) 2015-01-23 10:07:58 +01:00
Florent Kermarrec 261469814f add hack to generate verilog with AsyncResetSynchronizer (FIXME) 2015-01-23 03:18:25 +01:00
Florent Kermarrec fb7864c2b9 add missings __init__.py 2015-01-23 01:14:35 +01:00
Florent Kermarrec d45991d6eb fix README 2015-01-23 01:07:51 +01:00
Florent Kermarrec ea48f44b90 add LiteScopeLA example 2015-01-23 00:46:24 +01:00
Florent Kermarrec 5c40ff02cb add LiteScopeIO example 2015-01-23 00:15:42 +01:00
Florent Kermarrec f35f93a7c5 start refactoring and change name to LiteScope 2015-01-23 00:02:53 +01:00
Florent Kermarrec 609f8f9abb revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
Florent Kermarrec fadac0cf83 drivers: fix mask generation when using cond 2015-01-16 23:50:33 +01:00
Florent Kermarrec 8f14f67ea6 simplify UART2Wishbone and add timeout 2015-01-14 18:10:37 +01:00
Florent Kermarrec 54597f1bfc use new submodules/specials/clock_domains automatic collection 2015-01-14 13:55:18 +01:00
Florent Kermarrec 834e9b99be host/drivers: add possibility to pass cond dict to ease trigger pattern generation 2014-12-23 20:53:05 +01:00
Florent Kermarrec 8c5c32751e add input pipe stage option 2014-10-28 20:53:26 +01:00
Florent Kermarrec d860813dec use new direct access on endpoints 2014-10-16 17:57:30 +02:00
Florent Kermarrec 9649b1497c uart2wishbone: fix missing payload.d 2014-10-16 09:37:43 +02:00
Florent Kermarrec 2319ee0ab7 uart2wishbone: always use payload.d and not .d 2014-10-15 12:13:22 +02:00
Florent Kermarrec 027ddc65ca fill __init__.py to simplify imports 2014-10-10 17:24:36 +02:00
Florent Kermarrec bf95ea6c1c mila: simplify usage 2014-10-10 16:17:12 +02:00
Florent Kermarrec d0c9838dca uart2wishbone: share UARTRX and UARTTX with MiSoC 2014-10-10 15:15:58 +02:00
Florent Kermarrec ba30a01830 mila: fixes when used without RLE 2014-10-06 12:30:06 +02:00
Florent Kermarrec f72f11f7b4 mila: add clk_domain support
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.

future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
Florent Kermarrec 7043e6a5f3 mila: simplify export 2014-10-01 10:06:59 +02:00
Florent Kermarrec 111f527647 do some clean up 2014-09-24 22:26:33 +02:00
Florent Kermarrec 2fb418a373 use new MiSoC UART with phase accumulators
this will allow to speed up MiLa reads
2014-09-24 21:56:15 +02:00
Florent Kermarrec 452a4a76f3 use verilog namespace to export mila configuration 2014-08-03 17:09:01 +02:00
Florent Kermarrec 6ffed70b59 uart2wishbone: disconnect rx line from shared pads when bridge is selected
(avoid CPU crash when we communicate with the bridge)
2014-08-03 13:15:56 +02:00
Florent Kermarrec f4e6cebab2 clean up 2014-08-03 11:44:27 +02:00
Florent Kermarrec cd51e78f54 storage: use SyncFIFOBuffered to implement fifo in block ram 2014-08-02 19:12:03 +02:00
Florent Kermarrec 47a85cc1ad use new MiSoC fifo (no flush signal) 2014-08-01 10:36:15 +02:00
Florent Kermarrec a0df5baa55 host: add support for various csr_data width (8 & 32 tested, but should work with others) 2014-06-26 13:22:21 +02:00
Florent Kermarrec 0f9bc5ad6e fix bit inversion on CSV/PY exports 2014-06-21 19:06:47 +02:00