Florent Kermarrec
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2f7206b386
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sdram: revert use of scalar values for DFIInjector
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2015-03-03 09:09:54 +01:00 |
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Florent Kermarrec
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9df60bf98e
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lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
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2015-03-03 09:02:53 +01:00 |
Sebastien Bourdeauducq
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ff29c86fe1
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litesata/kc705: use FMC pin names
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2015-03-03 01:02:50 +00:00 |
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Sebastien Bourdeauducq
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8e48502d03
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spiflash: style
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2015-03-03 00:54:30 +00:00 |
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Sebastien Bourdeauducq
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2513833a24
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README: 80 columns
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2015-03-03 00:17:34 +00:00 |
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Sebastien Bourdeauducq
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69a0c597ad
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make.py: use ternary getattr
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2015-03-02 23:54:00 +00:00 |
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Florent Kermarrec
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410a162841
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sdram: disable by default bandwidth_measurement on lasmicon
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2015-03-02 19:53:16 +01:00 |
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Florent Kermarrec
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ca42611b6b
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README: add Pipistrello
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2015-03-02 19:18:46 +01:00 |
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Florent Kermarrec
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3449b7c933
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update README
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2015-03-02 18:41:03 +01:00 |
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Florent Kermarrec
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02ef1dc95a
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targets: fix mlabs_video FramebufferSoC
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2015-03-02 18:38:43 +01:00 |
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Florent Kermarrec
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473997df26
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cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
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2015-03-02 16:52:17 +01:00 |
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Florent Kermarrec
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8280acd3a7
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sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
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2015-03-02 12:17:49 +01:00 |
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Florent Kermarrec
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3465db25a7
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soc/sdram: be more generic in naming
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2015-03-02 11:55:28 +01:00 |
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Florent Kermarrec
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97331153e0
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sdram: create core dir and move lasmicon/minicon in it
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2015-03-02 11:38:22 +01:00 |
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Florent Kermarrec
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de698c51e4
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sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
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2015-03-02 11:29:43 +01:00 |
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Florent Kermarrec
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6b24562eea
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sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
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2015-03-02 10:59:43 +01:00 |
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Florent Kermarrec
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0980becb56
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sdram: improve memtest by adding 2 different writes/reads
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
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2015-03-02 10:52:22 +01:00 |
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Florent Kermarrec
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46020fd253
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sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
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2015-03-02 10:34:29 +01:00 |
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Florent Kermarrec
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c0b38e4905
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sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
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2015-03-02 09:18:32 +01:00 |
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Florent Kermarrec
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7300879b7f
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sdram: move dfii to phy
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2015-03-02 09:08:28 +01:00 |
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Florent Kermarrec
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9ad05b21ca
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sdram: fix remaining data_valid in dma_lasmi
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2015-03-02 09:05:18 +01:00 |
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Florent Kermarrec
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88e7fa21e4
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sdram: create test dir and move lasmicon/minicon tests to it
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2015-03-02 08:42:55 +01:00 |
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Florent Kermarrec
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b305b7828a
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sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
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2015-03-02 08:36:39 +01:00 |
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Florent Kermarrec
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6d83a112e6
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lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
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2015-03-01 22:04:27 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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4f37d29d05
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flash/spi: make bitbang optional (enabled by default)
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2015-03-01 17:15:22 +01:00 |
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Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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1e6d1deae8
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uart: add sim phy
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2015-03-01 16:52:50 +01:00 |
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Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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9e01bf5fdd
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litesata: create example design derived from SoC
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2015-03-01 11:33:38 +01:00 |
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Florent Kermarrec
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c21a7956c8
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liteXXX cores: remove Identifier duplication
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2015-03-01 11:24:58 +01:00 |
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Florent Kermarrec
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67ca0da1d9
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liteXXX cores: share same methodology for on-board tests
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2015-03-01 11:21:12 +01:00 |
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Florent Kermarrec
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7b464b2b1c
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litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
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2015-03-01 11:03:15 +01:00 |
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Florent Kermarrec
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32fce11edf
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litescope: avoid uart code duplication
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2015-03-01 10:07:55 +01:00 |
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Florent Kermarrec
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1b7f8d0439
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video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)
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2015-03-01 10:07:52 +01:00 |
Robert Jordens
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93b80b2f1c
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pipistrello: fix lpddr parameters, crg, flash, style
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2015-02-28 16:17:34 -07:00 |
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Florent Kermarrec
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144ee7ea9f
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soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
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Florent Kermarrec
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b32a0e6f9e
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liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
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2015-02-28 23:33:00 +01:00 |
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Florent Kermarrec
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b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
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liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
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liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
165a5b6760
|
soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
|
2015-02-28 20:04:51 +01:00 |
|
Florent Kermarrec
|
6107b7844a
|
test implementation on all targets and fix issues
|
2015-02-28 12:04:51 +01:00 |
|
Florent Kermarrec
|
1366ff5e26
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move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
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2015-02-28 11:51:51 +01:00 |
|
Florent Kermarrec
|
8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
|
Florent Kermarrec
|
69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
|
2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
912573f5c9
|
liteusb: move files and modify import to misoclib.com.liteusb
|
2015-02-28 11:18:00 +01:00 |
|
Florent Kermarrec
|
b647fe5823
|
merge liteusb
|
2015-02-28 11:16:16 +01:00 |