306235e93d
libcompiler_rt: add fixunsdfdi
2015-11-04 17:07:10 +08:00
1d60882f74
setup.py: fix version number
2015-11-04 16:47:02 +08:00
2de8e1de38
setup.py: consistent version number
2015-11-04 16:46:46 +08:00
1ea775efb6
conda: use correct branch
2015-11-04 16:46:28 +08:00
da171d8d0a
Merge 'new' branch
2015-11-04 16:41:34 +08:00
71fd951df2
integration/builder: add gateware toolchain path command line switch
2015-11-04 14:57:48 +08:00
db111a6eb0
software/makefiles: remove dependency system, make all always a phony target
2015-11-04 00:31:53 +08:00
c5dadf27ff
targets/pipistrello: add argparse functions consistent with kc705
2015-11-04 00:29:56 +08:00
421fe08770
targets/kc705: export generic argparse code
2015-11-03 18:46:34 +08:00
b340d7ec42
targets/kc705: make SDRAM controller type configurable
2015-11-03 18:45:58 +08:00
d554a06eba
interconnect/wishbone: fix CSRBank init
2015-11-03 18:45:23 +08:00
2520ab480b
wishbone: add read/write simulation methods
2015-11-03 10:37:31 +08:00
c9d203ab7f
Revert "conda: try to hack conda into checking out new branch directly"
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This reverts commit 1b11b7fa86
2015-11-02 12:30:52 +08:00
1b11b7fa86
conda: try to hack conda into checking out new branch directly
2015-11-02 12:28:43 +08:00
0cf4665d3a
travis: add dummy script
2015-11-02 11:52:42 +08:00
851067be51
conda: consistent version numbering
2015-11-02 11:52:28 +08:00
1e85f13133
add travis.yml
2015-11-02 11:20:26 +08:00
08ec92277e
add conda build scripts
2015-11-02 00:03:10 +08:00
2a818661e1
cores/dvi_sampler: fix imports
2015-11-01 22:38:06 +08:00
ca9631f7d3
interconnect/stream: add Converter (needs cleanup)
2015-11-01 22:15:28 +08:00
4707a25484
compiler_rt: add comparesf2
2015-10-24 22:54:44 +08:00
7459419ab4
cores/liteeth_mini: adapt all phys to new migen
2015-10-23 20:29:04 +02:00
0607e926c8
com/liteethmini/phy: remove use of FlipFlop in MII
2015-10-23 20:23:45 +02:00
197e5cf31c
cores: fix liteeth
2015-10-23 20:09:54 +02:00
766b0bee65
MANIFEST.in: fix lm32 data directory
2015-10-19 16:30:41 +08:00
e6452166c2
software: do not build libdyld and libunwind for lm32. Closes #22
2015-10-19 11:33:21 +08:00
884faedc00
integration/builder: escape backslash in makefile defines
2015-10-14 21:45:36 +08:00
93a615ade4
Merge branch 'new' of github.com:m-labs/misoc into new
2015-10-14 11:11:06 +08:00
ecc4c573eb
integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
...
Reported by Florent Kermarrec
2015-10-14 11:09:53 +08:00
f7787c3c13
software/bios: move romboot after serialboot and netboot
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On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 18:13:00 +02:00
9041868291
software/bios: move romboot after serialboot and netboot
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On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 17:49:29 +02:00
e96eba4493
setup: include software and Verilog files
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Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
2015-10-05 12:08:02 +08:00
c38d8175b7
interconnect/stream: add missing part of Demultiplexer
2015-10-05 00:10:55 +02:00
af3723db14
setup: add entry points
2015-10-05 00:45:02 +08:00
5e8c4cc364
setup: fix readme
2015-10-05 00:44:50 +08:00
9c905830dc
sdram: cleanup
2015-10-02 11:37:22 +08:00
d21358fc26
liteeth_mini: fix imports, replace Counter and FlipFlop
2015-09-30 20:17:52 +08:00
617c6ecb47
interconnect/stream: add multiplexer and demultiplexer
2015-09-30 19:43:51 +08:00
b3d5d1628c
interconnect/stream: remove param, do not depend on FIFO Record support
2015-09-30 16:40:34 +08:00
1b8f313d40
lasmicon: do not depend on FIFO Record support
2015-09-30 16:40:04 +08:00
c36029fa61
command line options support, CSR CSV, all targets building
2015-09-29 18:14:54 +08:00
e1927b7cbb
flterm: cleanup
2015-09-29 18:14:19 +08:00
48b6733c33
cores/gpio: fix import
2015-09-29 18:13:59 +08:00
dd7dfb0d5e
soc_core: simplify settings (assume CPU and CSR present)
2015-09-29 10:19:42 +08:00
b1a90053f5
minor fixes
2015-09-29 10:19:00 +08:00
8e860e3aba
Merge branch 'master' of github.com:m-labs/misoc
2015-09-28 20:40:37 +08:00
75d927e080
Revert "Sort constants in csr generation."
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This reverts commit d628c147ec
2015-09-28 20:40:31 +08:00
523377efbe
basic out-of-tree build support (OK on PPro)
2015-09-28 20:33:37 +08:00
bd7748299b
Fix typo.
2015-09-28 12:38:58 +03:00
e92d00f767
move software into misoc
2015-09-28 15:30:19 +08:00
Sebastien Bourdeauducq
Florent Kermarrec
whitequark