316faa7fa8
platforms/m1: resetless by default
2013-08-14 00:46:30 +02:00
4ebbfa63bf
add mist synthesis mode to build
2013-08-12 13:13:25 +02:00
88611be368
xilinx_ise: cleanup
2013-08-08 00:15:35 +02:00
9d531ba06a
Fix missing string replace. Added support for 32-bit ISE if 64-bit version is missing on 64-bit system.
2013-08-08 00:07:35 +02:00
6e64016885
add edif build routines
2013-08-03 10:55:12 +02:00
275a7ea94a
Change license to BSD
2013-08-01 17:46:09 +02:00
702471aa3c
platforms/mixxeo: new pin assignments to ease routing
2013-07-29 12:24:49 +02:00
f7f19b78e4
Fragment -> _Fragment
2013-07-26 15:13:24 +02:00
78776b4bc9
platforms/mixxeo: new pin assignments for 4 HDMI input ports
2013-07-21 15:55:31 +02:00
b18cffb5e8
xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior
2013-07-04 23:49:12 +02:00
05bc2885e9
Call finalize() after CRG creation
2013-07-04 19:49:39 +02:00
71c2c5813b
platforms/mixxeo: remove bank 3 DVI inputs
2013-07-04 19:27:28 +02:00
0883e99de3
Do not specify period constraints twice
2013-07-04 19:25:29 +02:00
0784cd164f
Add Mixxeo platform
2013-07-04 19:23:25 +02:00
1f3c941a78
platforms/m1: move generic platform commands to do_finalize
2013-07-04 19:22:59 +02:00
7e4552bbfc
lx9_microboard: improve compat with other boards
2013-06-27 19:30:57 +02:00
c1cf37f05a
add Avnet Spartan6 LX9 Micrboard platform
2013-06-27 19:18:47 +02:00
e233c62d27
* generic_platform.py: add a finalize() method
...
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
2013-06-27 19:17:02 +02:00
6b56428a21
Shorter multipin signal definition
2013-06-25 22:57:31 +02:00
953e603915
xilinx_ise: improve parameter passing
2013-06-01 17:22:57 +02:00
548f2685bb
platform/rhino: rename ismm data out signal to locked
2013-05-30 11:06:02 +02:00
759858f739
Use migen.fhdl.std
2013-05-26 18:07:26 +02:00
c13e573e9f
Require Python 3.3
2013-05-26 18:02:18 +02:00
e272e68fac
platforms/papilio_pro: swap tx/rx to be consistent with M1
2013-05-19 20:24:47 +02:00
fe64ade1ac
platforms/m1: add pots pins
2013-05-13 15:38:20 +02:00
7a2f31b2e8
platforms/papilio_pro: no reset signal by default
2013-05-07 19:10:18 +02:00
439f032921
crg: support for resetless system clock domain
2013-05-07 19:09:56 +02:00
6a4c194aab
platforms: add KC705
2013-05-07 10:31:12 +02:00
3d0894465c
mibuild: Add platform for Xilinx ML605 board
2013-05-06 14:21:56 +02:00
e4b0e8ed6d
xilinx_ise: enable register balancing
2013-05-06 14:21:39 +02:00
85e06cc100
xilinx_ise: implement NoRetiming synthesis constraint
2013-04-25 14:57:45 +02:00
bd0ae6592e
Add setup.py
2013-04-19 14:04:59 +02:00
6204bcfa10
README: fix quick intro
2013-04-19 14:00:46 +02:00
29eaf068f3
xilinx_ise: do not attempt to source settings file on Windows
2013-04-16 22:55:24 +02:00
31b1960188
xilinx_ise: add --no-source option to disable sourcing of ISE settings file
2013-04-16 22:39:35 +02:00
59d64e92e8
mibuild: define memory card pins of the Milkymist One platorm
...
This patch adds the memory card pins to the M1 platform definition in
mibuild.
I've tentatively named them "mmc". As far as I can tell, "MMC" is not
trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is
commonly used in the industry in a descriptive way to refer to this
sort of interface.
The original Verilog-based M1 calls the interface "mc", but since
several names have changed between milkymist and -ng, I thought I'd
use a more familiar name.
Usage example (clock signal divided by powers of two on the MMC TPs):
https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py
- Werner
2013-04-12 09:51:57 +02:00
843f8a5bfc
platforms: add Papilio Pro
2013-04-08 20:28:23 +02:00
715d332c3d
crg: apply constraint to IO pins, not internal signals
2013-04-08 20:28:11 +02:00
8cf7c96a53
crg: use new platform.request
2013-03-26 23:08:35 +01:00
38e92eb92b
altera_quartus: fix clock domain name
2013-03-26 23:05:46 +01:00
3b19dfc412
Support for platform info
2013-03-26 19:17:35 +01:00
74cc4d22cd
generic_platform: remove obj in request + add lookup_request
2013-03-26 17:56:53 +01:00
003f1950cd
xilinx_ise: fix clock domain names
2013-03-23 19:37:16 +01:00
797411c1a9
generic_platform: do not create clock domains during Verilog conversion
2013-03-18 18:44:58 +01:00
4bf3190244
MultiReg: remove idomain
2013-03-15 19:54:25 +01:00
6feb6e60b0
New clock_domain API
2013-03-15 18:46:11 +01:00
001beadb97
altera_quartus, de0nano: add copyright notices
2013-03-15 12:37:25 +01:00
f9e07b92a4
Added platform file for DE0 Nano (by Florent Kermarrec)
2013-03-15 11:41:38 +01:00
86d6f1d011
Added support for Altera Quartus (by Florent Kermarrec)
2013-03-15 11:32:12 +01:00
71c8172836
xilinx_ise/CRG_SE: reset inversion support
2013-03-15 11:31:36 +01:00
Sebastien Bourdeauducq
Nina Engelhardt
user
Nina Engelhardt
Robert Jordens
Florent Kermarrec
Brandon Hamilton
Werner Almesberger