Commit Graph

1620 Commits

Author SHA1 Message Date
Florent Kermarrec d45991d6eb fix README 2015-01-23 01:07:51 +01:00
Florent Kermarrec ea48f44b90 add LiteScopeLA example 2015-01-23 00:46:24 +01:00
Florent Kermarrec 5c40ff02cb add LiteScopeIO example 2015-01-23 00:15:42 +01:00
Florent Kermarrec f35f93a7c5 start refactoring and change name to LiteScope 2015-01-23 00:02:53 +01:00
Florent Kermarrec 7b2135f58f add .gitignore 2015-01-22 21:25:23 +01:00
Florent Kermarrec 4e3190120e fix build with upstream Migen/MiSoC 2015-01-22 21:23:14 +01:00
Florent Kermarrec 319a4a7f51 more doc 2015-01-22 21:04:36 +01:00
Florent Kermarrec b299116ace replace SATAX with sata_genx 2015-01-22 17:15:12 +01:00
Florent Kermarrec bbd2a076be targets/core: simplify ios generation 2015-01-22 16:52:26 +01:00
Florent Kermarrec 8d16a166c4 change submodules/specials/clock_domains syntax 2015-01-22 16:04:53 +01:00
Florent Kermarrec 609f8f9abb revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
Florent Kermarrec 3346bf8b2b frontend: simplify 2015-01-22 10:45:11 +01:00
Florent Kermarrec 8638e5dd15 doc: fix typos 2015-01-22 09:55:06 +01:00
Florent Kermarrec 97eb712766 bist: add random addressing 2015-01-22 01:56:37 +01:00
Florent Kermarrec 91bb531641 bist: add loops parameter for more precision in speed computation 2015-01-22 01:33:02 +01:00
Florent Kermarrec c9761be54f command: remove success/failed redundancy (keep failed) 2015-01-22 00:23:11 +01:00
Florent Kermarrec ff0c8e3d22 add PacketBuffer, simplify architecture and reduce ressource usage 2015-01-22 00:13:19 +01:00
Florent Kermarrec ebf1faed5b transport: simplify tx and reduce ressource usage 2015-01-21 19:11:54 +01:00
Florent Kermarrec 1b20831541 transport: simplify and reduce ressource usage 2015-01-21 18:55:42 +01:00
Florent Kermarrec fccf2c9430 common: clean up 2015-01-21 12:01:28 +01:00
Florent Kermarrec f0f6183c9a link/crc: use OrderedDict to generate the same code on each iteration 2015-01-21 11:48:06 +01:00
Florent Kermarrec 62bb5b47ca doc: fix .PNG extension 2015-01-21 11:11:01 +01:00
Florent Kermarrec 5825ec8f47 command: merge 2 states on tx 2015-01-21 10:52:56 +01:00
Florent Kermarrec d2ce266cba fix core generation 2015-01-21 10:52:18 +01:00
Florent Kermarrec 0af179f1f2 doc: add SATA description from Erik Landström's Thesis 2015-01-21 01:46:30 +01:00
Florent Kermarrec c70e8a3853 change copyright to HKU 2015-01-20 23:41:33 +01:00
Florent Kermarrec 578903bc11 manage reg_d2h errors 2015-01-20 19:28:56 +01:00
Florent Kermarrec d1e2f6d2b0 bist: show current length in MB 2015-01-20 15:24:52 +01:00
Florent Kermarrec 77778d24ae bist: add decoding of capabilities 2015-01-20 15:00:37 +01:00
Florent Kermarrec faef2319ad bist: decode more infos from identify data 2015-01-20 12:32:28 +01:00
Florent Kermarrec a5ae470ec9 fix license 2015-01-20 10:49:37 +01:00
Florent Kermarrec 0d77c780c6 copy README chapters to .rst 2015-01-19 23:28:14 +01:00
Florent Kermarrec 2bb9c6b649 add verilog backend to use the core with a "standard" flow 2015-01-19 20:38:48 +01:00
Florent Kermarrec d84ae7c80c clean up 2015-01-19 18:13:43 +01:00
Florent Kermarrec 18f2933d8b add doc skeleton (from emscripten with readthedocs theme) 2015-01-19 17:10:24 +01:00
Florent Kermarrec 79dbb6da4b replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows) 2015-01-19 09:45:34 +01:00
Florent Kermarrec 6de7e15a0c refactor code 2015-01-17 13:22:52 +01:00
Florent Kermarrec 6f2c7a236c add support of identify device command 2015-01-17 02:35:25 +01:00
Florent Kermarrec fadac0cf83 drivers: fix mask generation when using cond 2015-01-16 23:50:33 +01:00
Florent Kermarrec c227576f3d add test_link.py (replace test_bist_mila) 2015-01-16 21:16:05 +01:00
Florent Kermarrec 175618bcb4 use csr_data_width of 32 to speed up data mila upload 2015-01-16 20:57:01 +01:00
Florent Kermarrec 083bd54121 global clean up
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
2015-01-16 20:26:15 +01:00
Florent Kermarrec e90d97e9c2 phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed) 2015-01-16 19:25:35 +01:00
Florent Kermarrec d13366dd2d bist: use hardware counter for speed calc and remove loops mode 2015-01-16 18:48:34 +01:00
Florent Kermarrec 7ccc5f5274 link/cont: improve timing 2015-01-16 18:13:07 +01:00
Florent Kermarrec 1170a1070b add need_reset from controller to request system reset when SATA is not locked 2015-01-15 00:56:47 +01:00
Florent Kermarrec 8f14f67ea6 simplify UART2Wishbone and add timeout 2015-01-14 18:10:37 +01:00
Florent Kermarrec 788546c6ae add frontend and improve BIST 2015-01-14 15:47:13 +01:00
Florent Kermarrec 54597f1bfc use new submodules/specials/clock_domains automatic collection 2015-01-14 13:55:18 +01:00
Florent Kermarrec 62f55e32cf use new submodules/specials/clock_domains automatic collection 2015-01-12 13:14:26 +01:00