3922359ba1
test: Reinstate microwatt and neorv32
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They appear to be passing CI again.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2023-02-27 17:46:41 +10:30
93632465a0
Merge pull request #1540 from sensille/soc_odd_regions
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soc: allow regions that are not a power of 2
2023-02-24 10:30:47 +01:00
2abb419bee
Merge branch 'master' into soc_odd_regions
2023-02-24 10:30:34 +01:00
50822c080f
cores/gpio: Move self.ev.finalize after for loop.
2023-02-24 08:37:23 +01:00
8d3c03da08
Merge pull request #1613 from adamhlt/master
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Fix GPIO IRQ CSR generation
2023-02-24 08:36:18 +01:00
ce087640ed
Fix GPIO IRQ CSR generation
2023-02-23 17:08:08 +01:00
aef23c001a
README: Add first list of sponsors/partners.
2023-02-22 19:50:52 +01:00
51326b93a5
cpu/vexriscv: Fix missing add_soc_component update.
2023-02-21 10:37:09 +01:00
45b9636902
integration/soc: Avoid soc_region_cls workaround and update CPUs.
2023-02-21 09:43:17 +01:00
c1ee154340
global: Move Open definition to gen/common and use it.
2023-02-21 09:10:15 +01:00
653b74fe98
gen/fhdl/module: Fix typo.
2023-02-21 08:26:21 +01:00
22b61c39ca
cpu/rocket: Fix arch (thanks @gsomlo).
2023-02-20 19:28:23 +01:00
2274addd8f
cpu/rocket: Check/Fix opensbi region (thanks to @gsomlo).
2023-02-20 15:44:23 +01:00
a3fbd9794c
cpu/naxriscv: Generate CPU_MMU config based on xlen.
2023-02-20 15:12:43 +01:00
0f000a0a90
cores/cpu/json2dts: Add CPU_MMU config in cores and add initial NaxRisv support to json2dts.
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Also do minor cleanups by regrouping CPU parameters at the top.
2023-02-20 14:49:35 +01:00
019fac5653
cores/cpu: Switch to soc.bus.add_region instead or add_memory_region (now prefered).
2023-02-20 11:19:12 +01:00
01e9a54321
tools/litex_json2dts_linux: Add initial CLINT DTS generation.
2023-02-20 11:04:37 +01:00
ea308ea5b1
cpu/rocket: Use correct mapping for clint/plic.
2023-02-20 10:56:37 +01:00
e15e115170
cpu/rocket: Add initial dcache/icache/dtlb/itlb configs for .dts generation.
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Hardwired and probably incorrect, will need to be checked/fixed.
2023-02-20 10:47:09 +01:00
f2b0bf91eb
tools/litex_json2dts_linux: Switch from constants to configs.
2023-02-20 10:27:38 +01:00
f7d468dd1c
cores/cpus: Generate all CPU configs as LiteX configs (for consistency).
2023-02-20 10:27:10 +01:00
a5d9d309e5
tools/litex_json2dts_linux: Add intial Rocket support (just to allow .dts generation as basis, now will need to be adapted).
2023-02-20 10:17:23 +01:00
8c79c2599f
cpu/rocket/core: Initial changes for .dts generation through json2dts.
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For now just add information missing by json2dts to generate the .dts similarly to VexRiscv-SMP.
2023-02-20 10:13:16 +01:00
c6394c8f27
integration/builder: Add support for --soc-csv/--soc-json/--soc-svd arguments.
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Should be prefered over csr-xy since initial export was created when we were only interested
by CSR mapping export but has been extended since then to SoC mapping in general.
2023-02-20 09:34:30 +01:00
fbf63f2fc3
soc/cores/icap: Add UG570 reference and change _i/_o signal names.
2023-02-17 12:23:03 +01:00
9addd52990
soc/cores/esc: Add simple/initial ESC Dshot core supporting D150/300/600.
2023-02-17 09:29:16 +01:00
4fa0ea2fdb
Merge pull request #1598 from tpwrules/fix-litex-term
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tools/litex-term: completely eliminate multiprocessing
2023-02-16 21:17:53 +01:00
fa872cfae0
Merge pull request #1602 from antmicro/msieron/spd-fixes
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SDRAM SPD fixes
2023-02-16 21:06:54 +01:00
23d84bf5f5
liblitedram/sdram_rcd: fix no I2C case
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Remove send_stop parameter from the no-I2C case as well.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-02-16 15:40:07 +01:00
f84ecaf707
liblitedram/sdram_spd: do not send stop symbol
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According to the SPD specification, we shouldn't send
a stop symbol after the write that sets the address counter.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-02-16 14:35:00 +01:00
cdc1152162
liblitedram/sdram_spd: use temp_len when reading SPD
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This change should change anything from the point of view of
`sdram_read_spd` caller, but it makes it so less I2C reads are actually
hapenning.
With `len` we read too many bytes and write them to the `buf`.
In subsequent iterations we overwrite those bytes as all counters are
being updated by the `temp_len`. Nothing terrible, but too many
bytes were being read.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-02-16 14:30:23 +01:00
90f690ecce
README/BIOS: Bump year.
2023-02-16 09:10:01 +01:00
093c4fd166
tools/litex-term: completely eliminate multiprocessing
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Like commit 460fada3ac
2023-02-14 19:25:23 -06:00
106b2caaec
soc/cores/xadc: Fix refactoring issue (Zync -> Zynq :))
2023-02-13 15:43:43 +01:00
931b44ecd6
build/sim: Fix VIDEO flag generation.
2023-02-13 10:06:43 +01:00
44db314ddd
integration/soc/add_video_framebuffer: Add video_framebuffer region definition in linker.
2023-02-10 19:48:36 +01:00
3de5f20496
build/sim/litex_sim: Only compiles video module when used.
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Avoid additional SDL2 dependency for regular simulations.
2023-02-10 19:48:31 +01:00
1f08fe3286
build/sim/litex_sim: Add initial video module/support in simulation.
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Simulation with framebuffer:
litex_sim --with-sdram --with-video-framebuffer
Simulation with video terminal:
litex_sim --with-sdram --with-video-terminal
2023-02-10 19:48:24 +01:00
42f46c9c95
cpu/NaxRiscv fix nan-boxing on peripheral load
2023-02-10 17:21:53 +01:00
53e7492bd4
soc/cores/icap: Add clk_divider parameter and initial ICAPE3 support (Throught primitive parameters).
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Compiles on Ultrascale but still needs to be tested.
2023-02-10 16:19:42 +01:00
34422d2d91
cpu/NaxRiscv crt0.S now enable the FPU
2023-02-10 15:57:22 +01:00
ed48fb4d5d
tools/litex_client: Add --binary argument to display values in binary.
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Useful in some case to avoid decoding hexa manually.
2023-02-10 15:08:01 +01:00
5df1dacd18
cores/usb_ohci: Do minor review cleanups/changes.
2023-02-10 14:41:36 +01:00
d68bffb26e
Merge pull request #1597 from machdyne/master
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support multiple usb_ohci ports
2023-02-10 14:38:16 +01:00
211dfb2168
support multiple usb_ohci ports
2023-02-10 14:00:05 +01:00
2205a0c2c3
cores/xadc: Fix refactor issue.
2023-02-10 13:09:36 +01:00
408a68ba79
cores/dna: Add initial Ultrascale support.
2023-02-10 13:09:32 +01:00
b2053b7c52
cores/dna: Reduce default clk_divider to 2.
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To fix https://github.com/enjoy-digital/litex/issues/1516 .
2023-02-10 13:09:27 +01:00
838719c276
cores/xadc: Re-arrange and simplify code a bit.
2023-02-10 13:09:22 +01:00
8b36649c89
cores/xadc: Re-arrange and simplify code a bit.
2023-02-10 13:09:19 +01:00
Joel Stanley
enjoy-digital
Adam Henault
Michal Sieron
Thomas Watson
Victor Suarez Rovere
Dolu1990
inc