Commit Graph

5516 Commits

Author SHA1 Message Date
sadullah d15c911cac BlackParrot initial commit
w/ Litex BIOS simulation including LiteDRAM
w/ Litex BIOS working on FPGA excluding LiteDRAM
2020-01-16 19:13:02 -05:00
Florent Kermarrec 5aa516cb8d soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
2020-01-16 19:45:41 +01:00
Florent Kermarrec 862e784eae cpu/vexriscv: use 32-bit signal for externalResetVector 2020-01-16 16:20:25 +01:00
Florent Kermarrec f2a1673f46 targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection 2020-01-16 13:17:33 +01:00
Florent Kermarrec 990870d061 targets/genesys2: add EtherboneSoC 2020-01-16 12:32:59 +01:00
Florent Kermarrec 820e79bf9c platforms/de0nano: specify gpio for serial 2020-01-16 12:32:25 +01:00
Florent Kermarrec ba366d42d0 targets: cleanup EthernetSoC 2020-01-16 10:14:42 +01:00
Florent Kermarrec a26853702c soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. 2020-01-16 09:46:54 +01:00
Florent Kermarrec a168ecbabd targets/arty: add EtherboneSoC 2020-01-16 09:11:44 +01:00
Florent Kermarrec 7a4ecfa59d targets/kcu105: update 2020-01-15 13:17:59 +01:00
Florent Kermarrec 68e225fb45 test/test_targets: update 2020-01-15 13:09:03 +01:00
Florent Kermarrec 42efa99826 SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. 2020-01-15 10:59:01 +01:00
Florent Kermarrec 4050e60834 SoCCore: use hex for integrated_rom/sram_size 2020-01-13 20:01:45 +01:00
enjoy-digital f818755c9c
Merge pull request #339 from gsomlo/gls-csr-cleanup
CSR Improvements and Cleanup
2020-01-13 19:57:59 +01:00
Florent Kermarrec f1606dbc72 tools/litex_sim: use default integrated_rom_size 2020-01-13 17:39:23 +01:00
Florent Kermarrec 4648db0c2a cores/uart/UARTInterface: remove connect method 2020-01-13 16:58:00 +01:00
Florent Kermarrec 6c9f418d26 soc_core: fix uart stub 2020-01-13 16:56:31 +01:00
Gabriel Somlo b073ebadf6 bios/sdram: switch to updated CSR accessors, and misc. cleanup
Revert to treating SDRAM_DFII_PIX_[RD|WR]DATA CSRs as arrays
of bytes, but use the new uintX_t array accessors for improved
legibility, and to avoid unnecessary byteswapping.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Gabriel Somlo 2c39304110 software, integration/export: rename and reimplement CSR accessors
Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).

Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".

Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Florent Kermarrec 63cd23c9c3 cpu/vexriscv: revert mem_map_linux/main_ram 2020-01-13 16:02:32 +01:00
Florent Kermarrec 83a7225ccc SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
Florent Kermarrec 6e3f25a7e0 cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 2020-01-13 14:40:26 +01:00
Florent Kermarrec fe14b9cf86 targets/genesys2: update self.register_sdram 2020-01-13 14:39:45 +01:00
Florent Kermarrec 39ce39a298 soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. 2020-01-13 13:00:17 +01:00
Florent Kermarrec 23175190d8 cores/uart: add UARTCrossover 2020-01-13 10:14:38 +01:00
Florent Kermarrec 2f03d3234e cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover.
A bridged/crossover UART can now just be created by:
- passing uart_name="stream" to SoCCore/SoCSDRAM.
- adding a crossover UART core to the design:

# UART Crossover (over Wishbone Bridge
from litex.soc.cores.uart import UART
self.submodules.uart_xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.add_csr("uart_xover")
self.comb += self.uart.connect(self.uart_xover)
2020-01-13 09:20:40 +01:00
Florent Kermarrec d92bd8ffaa gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
enjoy-digital ff066a5e09
Merge pull request #338 from DurandA/master
Add optional 'ignore-loops' flag to nextpnr
2020-01-12 21:18:23 +01:00
Florent Kermarrec 26fe45fce1 cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" 2020-01-12 21:13:02 +01:00
enjoy-digital d40bf9d8a7
Merge pull request #340 from xobs/bridged-uart
uart: add BridgedUart
2020-01-12 20:40:27 +01:00
Sean Cross 5079a3c32e uart: add BridgedUart
This version of the UART adds a second, compatible UART after
the first.  This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-12 19:52:42 +10:00
Arnaud Durand d24a4b5428 Add optional 'ignore-loops' flag to nextpnr 2020-01-10 16:07:56 +01:00
Florent Kermarrec f70dd48279 bios/sdram: add memspeed 2020-01-10 14:25:46 +01:00
Florent Kermarrec fa22d6aa82 wishbone/Cache: avoid REFILL_WRTAG state to improve speed. 2020-01-10 14:25:07 +01:00
Florent Kermarrec f408527dd4 soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus.
Toolchain can be downloaded from https://toolchains.bootlin.com/
2020-01-10 08:49:34 +01:00
Florent Kermarrec 8889821c54 targets: sync with litex-boards 2020-01-09 21:12:00 +01:00
Florent Kermarrec aba8fc5c94 build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar.
Similar to the changes already applied to Xilinx backend.
2020-01-09 19:45:51 +01:00
enjoy-digital e318287ec2
Merge pull request #337 from gregdavill/spi-flash
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 13:24:17 +01:00
Greg Davill 49781467d7 soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging 2020-01-09 21:53:00 +10:30
Florent Kermarrec 2cf95e9f93 platforms/minispartan6: rename sd to sdcard and regroup data lines 2020-01-09 11:12:37 +01:00
Florent Kermarrec e99740e814 platforms/nexys4ddr: add sdcard pins 2020-01-09 11:00:54 +01:00
Florent Kermarrec 83ad674feb build/lattice/trellis: use a single fonction to parse device 2020-01-08 19:38:27 +01:00
enjoy-digital 018c7ca890
Merge pull request #336 from kbeckmann/trellis-speed
trellis: Pass speed argument to nextpnr
2020-01-08 19:17:04 +01:00
Konrad Beckmann 426ab676e8 trellis: Pass speed grade argument to nextpnr 2020-01-08 08:42:29 +01:00
enjoy-digital fd4cbd8053
Merge pull request #331 from betrusted-io/xadc_mods
WIP: add support for DRP on XADC
2020-01-06 18:09:12 +01:00
Florent Kermarrec 378722a7ef soc/cores/xadc: define analog_layout and simplify analog_pads connections 2020-01-06 16:28:48 +01:00
bunnie 87d456cae2 bring back analog_pads specifier, remove reset conditions on VP
For the "P" side of the analog channels, actually, connecting
a digital line to them has "no meaning". The docs say that
either you connect an analog pin to a pad, or vivado "ties it off
appropriately". I wish it were the case that tying a pin to 0 or 1
would actually connect it to a power or ground, because it means
that even in unipolar mode you have to burn two pins to break out
the signal of interest *and* the ground reference analog pad
(I thought I could just connect it to "0" and the pin would be
grounded, but that doesn't happen -- it's just ignored if it's
not wired to a pad).

For the pad specifier, is it OK to leave it with an optional
argument of analog_pads=None? I tried assigning to the
self.analog property after instantiation, but this doesn't
seem to work, the default values are preferred. It looks like
if you don't want to do the analog_pads= optional argument
the other way to do it would be to add code on the instiating
module that tampers with the properties of the instance directly,
but I think that's sort of ugly.

Also, I noticed you stripped out the layout specifier for
the analog_pads. I thought it would be nice to provide that
in the file, so the caller doesn't have to infer what the
pad layout is by reading the code...what's the motivation for
removing that?
2020-01-06 21:47:58 +08:00
Florent Kermarrec 642d073700 cpu/minerva: fix variant syntax warning 2020-01-05 21:04:27 +01:00
Florent Kermarrec 4dc0a61428 soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed. 2020-01-05 09:13:14 +08:00
enjoy-digital 8ba204c76f
Merge pull request #332 from gsomlo/gls-csr-mem-sel
interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)
2020-01-04 19:19:38 +01:00