Florent Kermarrec
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53c86e34f4
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build: ensure we return to working directory after building
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2015-11-30 13:33:39 +01:00 |
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Florent Kermarrec
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f6aeb6e41a
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soc/interconnect/stream: improve Pipeline to allow passing endpoints
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2015-11-28 18:31:47 +01:00 |
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Florent Kermarrec
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d85d2b7b9b
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soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
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2015-11-27 20:14:01 +01:00 |
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Florent Kermarrec
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c0539fff3e
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boards: add new digilent arty
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2015-11-27 00:29:30 +01:00 |
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Florent Kermarrec
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c24727ab4c
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soc/integration: allow using builder with soc.cpu_type == None
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2015-11-26 17:44:50 +01:00 |
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Florent Kermarrec
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7298fff1e6
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soc/interconnect/stream_packet: fix Counter removing
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2015-11-24 20:30:53 +01:00 |
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Florent Kermarrec
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8ebffc563a
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soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister
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2015-11-23 19:13:37 +01:00 |
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Florent Kermarrec
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254504e73f
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soc/integration/builder: export constants and memory_regions with csr_csv
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2015-11-23 19:12:58 +01:00 |
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Florent Kermarrec
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f6a2d5847a
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soc/tools/remote/client: make csr_csv parameter optional and default value to None
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2015-11-23 18:39:28 +01:00 |
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Florent Kermarrec
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6f4dd14ffa
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soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant
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2015-11-23 11:08:04 +01:00 |
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Florent Kermarrec
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cb22a207f1
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build/generic_platform: add support for int parameter for Pins (useful for core generation)
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2015-11-19 14:57:09 +01:00 |
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Florent Kermarrec
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8056653004
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soc/tools/remote/server: add --debug parameter
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2015-11-17 15:43:10 +01:00 |
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Florent Kermarrec
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6870707620
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soc/tools/remoter/server: fix exit on KeyboardInterrupt
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2015-11-17 15:31:23 +01:00 |
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Florent Kermarrec
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8ff31557c6
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soc/tools/remoter/server: add some printfs
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2015-11-17 15:18:46 +01:00 |
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Florent Kermarrec
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1a92489555
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soc/tools/remote: add comm_pcie and comm_udp (to be tested)
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2015-11-17 15:07:00 +01:00 |
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Florent Kermarrec
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d6fdd76930
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soc/tools/remote: small cleanup and remove csr_data_width from server side
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2015-11-17 11:35:22 +01:00 |
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Florent Kermarrec
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71483b8935
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soc/tools: initialize wishbone remote control (for now only uart)
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2015-11-17 01:05:52 +01:00 |
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Florent Kermarrec
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1cde84dccf
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soc/cores/uart remove software (will be re-written and will move to soc/tools)
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2015-11-16 17:07:22 +01:00 |
|
Florent Kermarrec
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1f80bb9561
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soc/interconnect/stream_packet: remove Counter
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2015-11-16 16:53:23 +01:00 |
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Florent Kermarrec
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ec35290c45
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soc/interconnect/wishbonebridge: remove Counter
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2015-11-16 16:48:37 +01:00 |
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Florent Kermarrec
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6fd0b73817
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build: remove edif support
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2015-11-16 16:26:38 +01:00 |
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Florent Kermarrec
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e407a1cdda
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gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign
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2015-11-16 16:18:09 +01:00 |
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Florent Kermarrec
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2f52d364af
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soc/interconnect/stream/SyncFIFO: expose fifo level
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2015-11-16 16:11:31 +01:00 |
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Florent Kermarrec
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7ed2576ce1
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soc/integration/cpu_interface: add bases, constants and memories output to csv files
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2015-11-15 00:04:44 +01:00 |
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Florent Kermarrec
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af909b43d5
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soc/cores/uart: add UARTWishboneBridgeDriver software
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2015-11-14 21:23:20 +01:00 |
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Florent Kermarrec
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3a2e6117f4
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soc/interconnect/stream: add Cast and others small fixes
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2015-11-14 12:17:09 +01:00 |
|
Florent Kermarrec
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041483dbe1
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soc/integration/builder: only copy Makefiles when not using symlinks
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2015-11-14 03:36:46 +01:00 |
|
Florent Kermarrec
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a2aa5726bf
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soc/cores: remove liteeth_mini and use liteeth
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2015-11-14 03:22:43 +01:00 |
|
Florent Kermarrec
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16ba646b1b
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add TODOs
|
2015-11-14 03:15:10 +01:00 |
|
Florent Kermarrec
|
cf4c7da2e7
|
fix soc/integration/soc_core.py
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2015-11-14 02:44:12 +01:00 |
|
Florent Kermarrec
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032f5a9620
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soc/interconnect: add stream_sim
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2015-11-14 00:43:49 +01:00 |
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Florent Kermarrec
|
ba959c832d
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soc/interconnect: rename packet to stream_packet
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2015-11-14 00:42:58 +01:00 |
|
Florent Kermarrec
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1158b98fdd
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doc: update logo
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2015-11-13 23:40:27 +01:00 |
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Florent Kermarrec
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fc3ffe87ac
|
for now use our fork of migen (to be able to simulate our designs)
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2015-11-13 18:31:46 +01:00 |
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Florent Kermarrec
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ae3d54499a
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litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
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2015-11-13 14:44:16 +01:00 |
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Florent Kermarrec
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7d6cee6751
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soc/interconnect/stream: add BufferizeEndpoints
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2015-11-12 18:54:15 +01:00 |
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Florent Kermarrec
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83427c87cd
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soc/interconnect/stream: add Pipeline
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2015-11-12 01:41:23 +01:00 |
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Florent Kermarrec
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81c6facca2
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soc/interconnect/stream: reintroduce params
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2015-11-12 01:12:15 +01:00 |
|
Florent Kermarrec
|
f6b30fcae2
|
soc/interconnect: add packet
|
2015-11-12 00:54:40 +01:00 |
|
Florent Kermarrec
|
525da89c7d
|
soc/interconnect: add wishbonebridge and uart bridge
|
2015-11-12 00:52:36 +01:00 |
|
Florent Kermarrec
|
89b189ce4a
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soc/interconnect/stream: reintroduce PipelinedActor/Buffer
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2015-11-12 00:51:32 +01:00 |
|
Florent Kermarrec
|
194e6137ae
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soc/integration/soc_core: add support for SoCs without CPU
|
2015-11-12 00:50:23 +01:00 |
|
Florent Kermarrec
|
57c0f85656
|
README: update
|
2015-11-11 17:38:12 +01:00 |
|
Florent Kermarrec
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c076c2cbd6
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boards/targets: remove papilio_pro/pipistrello
|
2015-11-11 17:38:03 +01:00 |
|
Florent Kermarrec
|
352cb91688
|
soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
|
2015-11-11 17:37:28 +01:00 |
|
Florent Kermarrec
|
1cec0f8086
|
boards/targets/sim: add ethernet support
|
2015-11-11 14:23:39 +01:00 |
|
Florent Kermarrec
|
1f6983da2c
|
soc/cores/liteeth_mini: add phy model for verilator simulation
|
2015-11-11 14:22:27 +01:00 |
|
Florent Kermarrec
|
481163b233
|
soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
|
2015-11-11 14:01:48 +01:00 |
|
Florent Kermarrec
|
d0ec57add6
|
doc: add logo
|
2015-11-11 13:36:29 +01:00 |
|
Florent Kermarrec
|
714a3d88e2
|
add LICENSE, update copyrights, add Migen install instructions
|
2015-11-11 13:22:39 +01:00 |