Florent Kermarrec
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6b24562eea
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sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
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2015-03-02 10:59:43 +01:00 |
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Florent Kermarrec
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46020fd253
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sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
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2015-03-02 10:34:29 +01:00 |
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Florent Kermarrec
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c0b38e4905
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sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
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2015-03-02 09:18:32 +01:00 |
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Florent Kermarrec
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7300879b7f
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sdram: move dfii to phy
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2015-03-02 09:08:28 +01:00 |
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Florent Kermarrec
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9ad05b21ca
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sdram: fix remaining data_valid in dma_lasmi
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2015-03-02 09:05:18 +01:00 |
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Florent Kermarrec
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88e7fa21e4
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sdram: create test dir and move lasmicon/minicon tests to it
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2015-03-02 08:42:55 +01:00 |
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Florent Kermarrec
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b305b7828a
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sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
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2015-03-02 08:36:39 +01:00 |
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Florent Kermarrec
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6d83a112e6
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lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
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2015-03-01 22:04:27 +01:00 |
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Florent Kermarrec
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4f37d29d05
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flash/spi: make bitbang optional (enabled by default)
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2015-03-01 17:15:22 +01:00 |
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Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
|
9e01bf5fdd
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litesata: create example design derived from SoC
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2015-03-01 11:33:38 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
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liteXXX cores: remove Identifier duplication
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2015-03-01 11:24:58 +01:00 |
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Florent Kermarrec
|
67ca0da1d9
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liteXXX cores: share same methodology for on-board tests
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2015-03-01 11:21:12 +01:00 |
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Florent Kermarrec
|
7b464b2b1c
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litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
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2015-03-01 11:03:15 +01:00 |
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Florent Kermarrec
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b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
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Florent Kermarrec
|
0fd1b9df8d
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liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
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liteXXX cores: update README and doc
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2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
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Florent Kermarrec
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8e67d6e69f
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:08:17 +01:00 |
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Florent Kermarrec
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0dfca49e68
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litesata: move file and modify import to misoclib.mem.litesata
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2015-02-28 11:03:24 +01:00 |
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Florent Kermarrec
|
b6358be0a1
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merge litesata
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2015-02-28 10:48:08 +01:00 |
|
Florent Kermarrec
|
2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |