Commit Graph

35 Commits

Author SHA1 Message Date
Florent Kermarrec 6771ed0796 ci: migrate from Travis CI to Github Actions. 2020-11-24 15:55:49 +01:00
Florent Kermarrec 77ae243310 test: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:40:21 +02:00
Florent Kermarrec 5d202ddb97 test: update. 2020-06-02 13:51:48 +02:00
Florent Kermarrec 80ec5eca76 boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform. 2020-06-02 12:18:12 +02:00
Mariusz Glebocki 7434376c07 test/test_targets: add arty_symbiflow
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:56 +02:00
Florent Kermarrec 3d06dc028c test/test_targets: update build_test. 2020-05-22 08:42:02 +02:00
Florent Kermarrec 9f941138d2 test/test_targets: workaround to fix travis. 2020-05-13 11:04:40 +02:00
Florent Kermarrec 98d1b45157 platforms/targets: fix CI. 2020-05-05 15:55:09 +02:00
Florent Kermarrec c154d8d2fc test/test_targets: remove versa_ecp3. 2020-03-25 08:47:43 +01:00
Florent Kermarrec f03d862c06 targets: switch to add_ethernet method instead of EthernetSoC. 2020-03-20 23:46:15 +01:00
Florent Kermarrec 54fb3a61cd test/test_targets: use uart-name=stub. 2020-02-29 11:07:10 +01:00
Florent Kermarrec 7b92a17c6e test/test_targets: limit max_sdram_size to 1GB 2020-01-17 13:24:45 +01:00
Florent Kermarrec 68e225fb45 test/test_targets: update 2020-01-15 13:09:03 +01:00
Florent Kermarrec 650df0ebc2 test/test_targets: skip Minerva test on Travis-CI, remove commented tests 2019-10-28 11:00:08 +01:00
Florent Kermarrec 63a813af9c soc_core: fix cpu_type=None case and add test for it 2019-09-30 08:26:38 +02:00
Florent Kermarrec 241c3c642b test/test_targets: update cpu-type to mor1kx 2019-09-29 17:12:15 +02:00
Florent Kermarrec dc03b7fab9 boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00
Florent Kermarrec c7f36ab08f test: add copyright header 2019-06-23 23:31:11 +02:00
Florent Kermarrec 55ebcc00eb test/test_targets: add de10lite 2019-06-05 20:03:19 +02:00
Florent Kermarrec b300c32103 test/test_targets: add de2_115, de1soc 2019-06-02 19:22:09 +02:00
Florent Kermarrec 745d83a332 boards: add initial NeTV2 support (clocks, leds, dram, ethernet) 2019-05-10 18:55:40 +02:00
Florent Kermarrec 3ee9ce0529 test/test_targets: fix test_ulx3s name 2019-05-09 11:48:57 +02:00
Florent Kermarrec 74d37465b3 test/test_targets: comment bad variant tests for now 2019-04-29 17:11:42 +02:00
Tim 'mithro' Ansell 5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Florent Kermarrec f7c0b118ce test/test_targets: cover all platforms 2019-04-23 11:38:18 +02:00
Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
Florent Kermarrec 28d80bd641 ci: fix test_targets/test_simple 2019-04-22 08:53:43 +02:00
Florent Kermarrec e98ac680c1 travis: simplify, enable and add RISC-V toolchain to build targets 2019-04-22 08:32:00 +02:00
Florent Kermarrec 68e1dfca28 boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
Florent Kermarrec 5137c2bf88 test/test_targets: update 2018-11-17 17:36:57 +01:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec b4ebfb4031 test/test_targets: check top.v generation 2017-04-24 19:25:58 +02:00
Florent Kermarrec 35e3d93d9b test: add basic test_targets.py 2017-04-24 19:13:17 +02:00