46788f2d9c
integration/soc Add accessible_region to add_memory_buses
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Enables CPUs to know which memory addresses are accessible via
the connected memory_bus.
2022-07-04 12:47:09 +02:00
8eae77a310
Merge pull request #1347 from enjoy-digital/ci-cpus
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test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:52:27 +02:00
7388684232
integration/export/get_memory_x: Replace spi_flash with rom.
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Even when ROM is stored in SPI Flash, ROM regions has to be created.
2022-06-29 11:19:52 +02:00
9c3663f3d2
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:15:48 +02:00
bc6ce4b04b
Merge pull request #1346 from cklarhorst/master
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build/xilinx/ise: Fix yosys flow
2022-06-29 10:16:06 +02:00
aec8cd5339
build/xilinx/ise: Fix yosys flow
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The top name changed in 2016 but only XST was changed.
2022-06-28 15:26:14 +02:00
ec9d1c4fd0
CI: Disable more CPUs.
2022-06-27 22:43:01 +02:00
f898423390
test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator.
2022-06-27 19:54:50 +02:00
60d0c4ddd4
ci: Compile/Install Verilator from sources (Required for updated Vexriscv-SMP).
2022-06-27 18:53:02 +02:00
4ff839900b
bios/cmd_litedram: Enable sdram_init/mr_write commands also for SDRAM.
2022-06-27 17:49:39 +02:00
c4e3962def
soc/add_etherbone: Expose IP Broadcast capability.
2022-06-27 15:46:57 +02:00
e4c81e8fdf
Merge pull request #1338 from p-woj/litesdcard-init
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software/liblitesdcard: Fix condition in sdcard_init
2022-06-22 19:42:23 +02:00
ee1af96ab7
CHANGES: Update.
2022-06-22 18:13:49 +02:00
e141826fd8
software/liblitesdcard: Fix condition in sdcard_init
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Instead of retrying `sdcard_app_send_op_cond` until it returns an error,
retry until it completes successfully and the command response has the
busy bit set.
2022-06-22 14:44:28 +02:00
1a90549fa3
interconnect/axi/axi_full: Switch to our own AXI Interconnect (Shared & Crossbar).
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We were not able to simulate verilog_axi interconnect/crossbar correctly since to what
seems to be a simulation mismatch. The code also seems to requires fixing some synthesis
issues with Yosys. When tested with Vivado, the SoC was also miss-behaving (not booting
correctly).
The simulation mismatch issue is logged here: https://github.com/enjoy-digital/litex_verilog_axi_test/issues/1
Since we already had our own AXI-Lite interconnect, creating our AXI interconnect can be
largely based on it with only minor modifications, so switch to it. This also allow simplification
in the interconnect selection/instance.
2022-06-20 19:51:31 +02:00
573479b395
interconnect:axi/axi_lite/interconnect: Cosmetic cleanups.
2022-06-20 19:13:44 +02:00
bb1702e6d5
integration/export: Align MEM_REGIONS for BIOS display with mem_list.
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Before:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x01000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0x82000000 0x10000
After:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x10000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0xf0000000 0x10000
2022-06-20 15:21:16 +02:00
b00d22f56a
Merge pull request #1334 from antmicro/move_to_f4pga
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Move from deprecated Symbiflow to F4PGA
2022-06-20 11:56:42 +02:00
b8ee713dba
Merge pull request #1331 from cr1901/gowin-win
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Gowin: Fix `copyfile` paths
2022-06-20 11:32:47 +02:00
b66bd171cc
litex_setup: Use recursive clone for litex_verilog_axi.
2022-06-20 11:23:00 +02:00
32d1589fb8
litex_setup: Move valentyusb to Misc Cores and also install litex_verilog_axi.
2022-06-20 11:01:47 +02:00
9b6c9e6630
litex_setup: Switch to specific branch when initializing repositories.
2022-06-20 10:43:30 +02:00
ef2f1bd65b
Merge pull request #1333 from gsomlo/gls-noboot-warning
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bios/main: Wrap CONFIG_NO_BOOT around boot_sequence()
2022-06-20 08:37:03 +02:00
b86629a615
Merge pull request #1335 from benstobbs/valentyusb-proper-install
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Move valentyusb install to litex_setup.py
2022-06-20 08:36:44 +02:00
ca97d91424
clone correct valentyusb branch
2022-06-19 12:58:01 +01:00
db3fa1efc7
move valentyusb install to litex_setup.py
2022-06-19 12:51:14 +01:00
cbd873a33e
test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
839ca545a4
build: quicklogic: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
2c0f59536c
build: xilinx: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
0941459061
integration/soc: Add initial AXI-full support.
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Main bus can now be switched to AXI-full with --bus-standard=axi.
The interconnect will be AXI-Full (Using Alex Forenchich's verilog_axi
Interconnect and Crossbar) but ROM/SRAM will still be in AXI-Lite (Will
be switched to AXI-full in the future).
This gives a first working version that can be used for further improvements.
Note that the interconnect can also be selected by --bus-interconnect=shared or
crossbar.
2022-06-17 16:21:31 +02:00
8394e93742
interconnect/axi/axi_full: Add AXI Interconnect (Shared and Crossbar).
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For now reusing Alex Forenchich's modules wrapped with LiteX.
2022-06-17 16:07:05 +02:00
bc667c6456
interconnect/axi/axi_full/AXIInterface: Add name/bursting parameters.
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To add compatibility with AXILiteInterface and allow dynamic selection.
2022-06-17 16:04:25 +02:00
333aadbf6e
integration/soc/SoC: Switch to finalize and finalize submodule only at the end.
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This avoid elaborating submodules before adding the final modules and gives more
flexibility.
2022-06-17 16:01:28 +02:00
4c0a943996
interconnect/axi: Create axi directory and split code by type/functionnality.
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AXI code is now too large to be contained in a single file, splitting code by type/functionnality
will simplify future additions.
2022-06-16 18:53:12 +02:00
c4e07e2a5b
integration/soc: Allow Bus Interconnect to use either InterconnectShared or Crossbar and add --bus-interconnect command line parameter.
2022-06-16 17:47:13 +02:00
6942e3240c
interconnect/axi/AXIDownConverter: Switch to AXI-Full (Inspired from AXIUpConverter).
2022-06-16 16:16:49 +02:00
f9f3557bca
bios/main: Wrap CONFIG_NO_BOOT around boot_sequence()
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This eliminates a "defined but unused" warning on the
`boot_sequence()` function when `main.c` is compiled
with `#define CONFIG_NO_BOOT`.
2022-06-16 08:22:14 -04:00
50553a45ec
integration/soc/add_adapter: Create data_width_convert/bus_standard_convert functions and improve code genericity.
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This already cleanup/simplify code and will also allow eventual order changes in the conversions.
2022-06-16 11:53:47 +02:00
3e10576fcd
build/gowin: Fix bitstream copy to gateware directory.
2022-06-15 21:45:19 -04:00
b6f4302e8e
integration/soc/add_adapter: Add AXI2AXILite and AXI2Wishbone support.
2022-06-15 19:37:04 +02:00
da5d9ecf9b
interconnect/axi: Add AXIDownConverter (through AXI-Lite) and AXIConverter.
2022-06-15 19:34:47 +02:00
ac800da43c
cpus: Make use of new automatic AXI <-> AXI-Lite/Wishbone conversion.
2022-06-15 18:15:59 +02:00
d7e599c04f
integration/soc/add_adapter: Add AXI<->Wishbone and AXI<->AXI-Lite support.
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Allow directly passing AXI interfaces to add_slave/add_master and thus simplify user code.
2022-06-15 17:58:39 +02:00
f62ba0f66d
integration/soc: Simplify add_config and use it for all config parameters.
2022-06-15 17:34:07 +02:00
1d7aa9c438
cpu/openc906: Switch to AXI-Lite instead of Wishbone and minor cleanup.
2022-06-15 16:51:50 +02:00
eebb639c12
Merge pull request #1328 from Icenowy/c906
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[WIP] soc/cores/cpu: add initial OpenC906 support
2022-06-15 11:23:14 +02:00
8fa9178716
Merge pull request #1326 from Technosystem-Labs/openocd_0_11
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Updated OpenOCD stream for expr use
2022-06-15 11:10:02 +02:00
a4de315772
Merge pull request #1329 from Icenowy/altpll-fix
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Misc fixes to Altera PLL support
2022-06-15 10:52:24 +02:00
d1a456a545
integration/export/_get_csr_addr: Add back parenthesis around CSR_BASE + X.
2022-06-14 15:03:18 +02:00
8ffabe3bcb
soc/cores/cpu: add initial OpenC906 support
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It's only boot tested in sim and build tested in Vivado now, and it
requires a FPGA > 100k LUT4 (XC7A100T currently does not fit).
The ISR code is based on Rocket one.
These Python code depends on a forked version of OpenC906 at [1].
[1] https://github.com/Icenowy/openc906/tree/fpga-optimization
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-14 02:04:58 +08:00
Christian Klarhorst
enjoy-digital
Piotr Wojnarowski
Ben Stobbs
Robert Szczepanski
Gabriel Somlo
William D. Jones
Icenowy Zheng