Sebastien Bourdeauducq
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a99c2acfa8
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Remove explicit bus names and rely on the new automatic namer
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2012-01-27 22:20:57 +01:00 |
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Sebastien Bourdeauducq
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076c171c7b
|
Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
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Sebastien Bourdeauducq
|
20425703fa
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Wishbone: omit fixed LSBs
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2012-01-13 17:29:05 +01:00 |
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Sebastien Bourdeauducq
|
ba40f58491
|
corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
|
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
92f24b784d
|
wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
|
923fc52e68
|
wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
|
4d1a960308
|
wishbone: decoder + shared bus interconnect
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2011-12-09 13:11:52 +01:00 |
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Sebastien Bourdeauducq
|
5c7131dc86
|
wishbone: arbiter
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2011-12-08 23:21:25 +01:00 |
|
Sebastien Bourdeauducq
|
7c99e51b90
|
Named buses
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2011-12-08 19:16:08 +01:00 |
|
Sebastien Bourdeauducq
|
5720a51dad
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wishbone: add missing SEL
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2011-12-08 19:09:32 +01:00 |
|
Sebastien Bourdeauducq
|
c43f3da534
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Wishbone declarations
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2011-12-08 18:47:41 +01:00 |