477e51849a
cores/prbs: Add a 'wrap' option to PRBSRX
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If enabled, then the error count wraps around when it
reaches the limit of the 32b counter instead of saturating
to a max value.
Software can then detect the wrap and act accordingly.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-12-13 19:46:06 +01:00
e50ff33c6e
test/test_cpu: Disable Minerva test for now.
2021-12-13 16:51:23 +01:00
cec83a5dd8
Merge pull request #1131 from fjullien/efinix_titanium_support
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Efinix titanium support
2021-12-13 15:44:04 +01:00
40c001d522
check calculated PLL frequencies against user's values
2021-12-13 14:47:57 +01:00
eafee9dac5
efinix: add Titanium PLL support
2021-12-13 14:47:49 +01:00
148d124d03
efinix: get family name from device name
2021-12-13 14:36:54 +01:00
f37188c358
efinix: add more valid IOStandard
2021-12-13 14:34:08 +01:00
12e5443489
efinix: fix efxpt:single_conn parsing
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Sometimes instance can be this form:
<efxpt:single_conn ... instance="GPIOT_PN_16.lvttl1,...
This patch handle this case
2021-12-13 14:31:34 +01:00
92f5a9f0e6
soc/cores/led/WS2812: Add Bus Mastering capability.
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Useful on small FPGAs to reduce resource usage: When enabling bus mastering,
the core is able to automatically read led values from the bus and can then
avoid the internal memory. This is particularly useful when reading values
from SPI Flash with a small "Player" core just updating the base address.
2021-12-12 15:18:24 +01:00
649c45e962
Merge pull request #1128 from gregdavill/fatfs-alignment-fix
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software.fatfs: Align fatfs sector buffers
2021-12-10 21:54:34 +01:00
65a8249f4b
Merge pull request #1130 from whitequark/master
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litex_setup: nMigen has been renamed to Amaranth HDL
2021-12-10 21:43:04 +01:00
9329d3f092
litex_setup: nMigen has been renamed to Amaranth HDL.
2021-12-10 17:41:30 +00:00
d108d2ad3d
tools/litex_json2dts_linux.py: update mmc node
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Add `reg-names` property, which facilitates cleaner probing
for the upstream Linux device driver. Also, add a reference
to the LiteX sys_clk, also for the benefit of the upstream
driver, which can't rely on the CPU frequency matching sys_clk.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-12-10 11:05:58 -05:00
b4fb3ea981
tools/litex_json2dts_linux.py: update clock specification
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Remove `bus-frequency` property from `soc` node. Instead,
create a separate `clocks` section containing a node to
represent the LiteX sys_clk, which may be referenced from
other peripherals if needed.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-12-10 11:02:35 -05:00
416886c723
software.fatfs: Align fatfs sector buffers
2021-12-10 17:27:26 +10:30
230ba5f7ba
cpu/gowin_emcu: Minor cosmetic cleanups, add copyright.
2021-12-09 16:01:41 +01:00
7286f95f55
Merge pull request #1125 from fjullien/efinix_add_bank_voltage
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efinix: add io bank voltage configuration
2021-12-09 14:26:33 +01:00
435e16c421
Merge pull request #1126 from sergachev/feature/gowin_emcu
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Add initial Gowin EMCU support
2021-12-09 14:25:04 +01:00
db83b38a2a
cores/cpu: add initial Gowin EMCU support
2021-12-08 23:51:57 +01:00
18a1d74cf6
soc/interconnect: add basic ahb support
2021-12-08 23:08:45 +01:00
5efb64b80b
efinix: add io bank voltage configuration
2021-12-08 18:04:11 +01:00
9482cbc85d
soc/add_pcie: Expose more DMA parameters.
2021-12-08 08:21:09 +01:00
d3b493d4e8
Merge pull request #1124 from tcal-x/cfu-finalize
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Defer adding the CFU instance until cpu.do_finalize().
2021-12-07 18:34:09 +01:00
96b3587225
Merge pull request #1123 from LazyDodo/master
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build/altera: fix rbf generation on windows
2021-12-07 18:33:13 +01:00
85a3b00d1f
Defer adding CFU instance until cpu.do_finalize().
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Signed-off-by: Tim Callahan <tcal@google.com>
2021-12-07 00:09:59 -08:00
235e55c9af
build/altera: fix rbf generation on windows
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Testing for a file existing is slightly different
between bash and .bat files which caused the batch
file to error out.
2021-12-06 09:39:19 -07:00
cdaf8af555
Merge pull request #1121 from gregdavill/dram-rank-fix
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soc.intergration.dram: Use nranks in capacity calc
2021-12-06 10:33:09 +01:00
4679b86314
soc.intergration.dram: Use nranks in capacity calc
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This ensures that dual ranked memory appears with the correct capacity
2021-12-05 15:34:24 +10:30
d9c44c46ab
cores/clock/gowin_gw1n: Add back GW1NR support.
2021-12-02 18:22:42 +01:00
e6f316d0f4
Merge pull request #1115 from sergachev/master
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Improve Gowin clock primitive support
2021-12-02 09:13:31 +01:00
b8710e44b8
build/efinix: Fix VHDL support.
2021-12-01 08:32:49 +01:00
c5cd2e55e6
Merge pull request #1116 from lschuermann/dev/sim-remove-ifg-debug
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litex_sim/xgmii: remove IFG SUFFICIENT debug message
2021-11-30 16:07:49 +01:00
5e851bd09e
Merge pull request #1117 from enjoy-digital/gpio_tristate
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cores/gpio/GPIOTristate: Allow passing platform resource with subsignals directly.
2021-11-30 16:07:22 +01:00
16a43e983e
cores/gpio/GPIOTristate: Use Record.flatten() instead of Record.raw_bits().
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Fix verilog syntax error.
2021-11-30 15:48:34 +01:00
9036050364
cores/gpio/GPIOTristate: Allow passing platform resource with subsignals directly.
2021-11-30 15:32:48 +01:00
c18635ad19
litex_sim/xgmii: remove IFG SUFFICIENT debug message
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Removes a leftover debug message for validating correct XGMII IFG DIC
behavior. Useful for development, but gets annoying quickly while
running the simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-30 14:19:12 +01:00
aebef65932
build/generic_platform/add_source: Tranform filename to absolute path earlier to catch duplications when relative/absolute paths are used in design.
2021-11-29 14:17:58 +01:00
f2319d39d4
Merge pull request #1114 from andykitchen/femtorv-reset-fix
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fix FemtoRV reset signal
2021-11-29 08:07:13 +01:00
facb278ef8
Merge pull request #1113 from shenki/microwatt-xilinx-multiplier
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microwatt: Use Xilinx multiplier
2021-11-29 08:04:57 +01:00
24ec49db2e
microwatt: Use Xilinx multiplier
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Use the technology specific multiplier implementation when building for a
Xilinx platform.
This isn't understood by yosys so we can't use it when yosys is used for
synthesis.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-29 15:30:19 +10:30
2562ae5f63
fix FemtoRV reset signal
2021-11-28 22:35:46 +11:00
f743dd3873
cores/clock/gowin: merge GW1NS PLL support into GW1N; add more details to PLL frequency ranges
2021-11-28 11:59:36 +01:00
0503188661
litex_setup/riscv_gcc_toolchain_download: Add Fedora support (get linux-centos6).
2021-11-26 14:21:26 +01:00
85d6cb4b8d
build/anlogic: Minor cosmetic cleanups.
2021-11-23 19:12:31 +01:00
c2d6ea97fa
Merge pull request #1111 from mmicko/anlogic
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Add initial support for Anlogic devices
2021-11-23 19:02:16 +01:00
fac2b2a9fb
Add initial support for Anlogic devices
2021-11-22 19:08:58 +01:00
aecfbc0609
cpu/femtorv/core: Fix standard variant march.
2021-11-22 09:34:38 +01:00
440ef4e2b5
cpu/femtorv/core: Fix petitbateau's march (rv32imfc).
2021-11-22 09:12:45 +01:00
a96304e287
cpu/femtorv/core: Generate gcc_flags from GCC_FLAGS/Variants.
2021-11-22 09:10:04 +01:00
828f763b48
Merge pull request #1100 from lschuermann/dev/sim-xgmii-ethernet-ifg
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sim/xgmii_ethernet: fix XGMII start of frame char handling and RX IFG insertion (with optional DIC)
2021-11-21 19:19:46 +01:00
Sylvain Munaut
Florent Kermarrec
Franck Jullien
whitequark
Gabriel Somlo
Greg Davill
Ilia Sergachev
Tim Callahan
Ray Molenkamp
Andrew Dennison
Leon Schuermann
Joel Stanley
Andy Kitchen
Miodrag Milanovic