Sebastien Bourdeauducq
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4c040810bc
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Merge branch 'master' of github.com:milkymist/migen
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2012-01-05 19:27:55 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
Alain Péteut
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6bd8566c48
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setup.py: fix to catch all modules
Signed-off-by: Alain Péteut <peteut@space.unibe.ch>
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2011-12-27 11:19:37 +01:00 |
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Alain Péteut
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5f53e6473a
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Add setup script
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2011-12-24 13:46:40 +01:00 |
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Sebastien Bourdeauducq
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1ce4fbdb98
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example: flow conversion
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2011-12-23 00:36:07 +01:00 |
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Sebastien Bourdeauducq
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edf90870c2
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flow: sum and division actors
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2011-12-23 00:35:53 +01:00 |
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Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
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Sebastien Bourdeauducq
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f0aac4b50f
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flow: actor class
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2011-12-22 19:37:16 +01:00 |
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Sebastien Bourdeauducq
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566295dea3
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csr: use optree
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2011-12-22 19:36:56 +01:00 |
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Sebastien Bourdeauducq
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ba40f58491
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corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
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Sebastien Bourdeauducq
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8a394f9159
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verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
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26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
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Sebastien Bourdeauducq
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7456195775
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Consistent names
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2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
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47d321cd75
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README: Flow
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2011-12-20 00:07:46 +01:00 |
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Sebastien Bourdeauducq
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d9dc604c99
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README: Core Logic, Bus, Bank
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2011-12-19 23:24:31 +01:00 |
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Sebastien Bourdeauducq
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7774ace7e1
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README: structure + FHDL description
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2011-12-19 22:15:10 +01:00 |
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Sebastien Bourdeauducq
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3b640c45bb
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Use new syntax
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2011-12-18 22:02:05 +01:00 |
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Sebastien Bourdeauducq
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af0a03b65f
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examples: remove old-style declarations
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2011-12-18 21:54:39 +01:00 |
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Sebastien Bourdeauducq
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94c5fba067
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corelogic: fix signal exports
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2011-12-18 21:54:28 +01:00 |
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Sebastien Bourdeauducq
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4f4d809a4e
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fhdl: better matching of assignment
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2011-12-18 21:49:48 +01:00 |
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Sebastien Bourdeauducq
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107f03fd4b
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Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
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Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
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Sebastien Bourdeauducq
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41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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135a2eb868
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bank: support raw registers
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2011-12-18 00:28:04 +01:00 |
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Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
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Sebastien Bourdeauducq
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1a845d4553
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32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
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Sebastien Bourdeauducq
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bb21f7584a
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32-device, 8-bit CSR bus
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2011-12-17 15:54:42 +01:00 |
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Sebastien Bourdeauducq
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1b3edd07ca
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norflash tb: use get_fragment
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2011-12-17 15:22:26 +01:00 |
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Sebastien Bourdeauducq
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6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
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0e30d67fa3
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Multiply system clock
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2011-12-17 15:00:18 +01:00 |
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Sebastien Bourdeauducq
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85fbe07b94
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clkfx module
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2011-12-17 15:00:11 +01:00 |
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Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
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Sebastien Bourdeauducq
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738b45dcbd
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Support the new FHDL syntax
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2011-12-16 21:30:22 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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929cc98070
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wishbone2csr: wait for WB deack
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2011-12-13 17:38:59 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |
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Sebastien Bourdeauducq
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22d03b4943
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timeline: only trigger in rest state
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2011-12-13 15:25:46 +01:00 |
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Sebastien Bourdeauducq
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6f7a35e0a3
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examples: Wishbone interconnect test bench
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2011-12-13 14:10:56 +01:00 |
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Sebastien Bourdeauducq
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c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
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Sebastien Bourdeauducq
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92f24b784d
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wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
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0ea7a9b2e6
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wishbone2csr: fix double-write bug
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2011-12-13 00:25:46 +01:00 |
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Sebastien Bourdeauducq
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923fc52e68
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wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
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a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |