Commit Graph

1462 Commits

Author SHA1 Message Date
Florent Kermarrec 2fa28c1b5d mac: add padding 2015-02-22 13:56:06 +01:00
Florent Kermarrec a802a5c535 remove MiSoC dependency 2015-02-21 23:50:25 +01:00
Florent Kermarrec a2370388fb doc: remove IP 2015-02-21 23:34:30 +01:00
Florent Kermarrec 15240912c9 doc: remove IP 2015-02-21 23:34:08 +01:00
Florent Kermarrec ea7962da12 doc: remove IP 2015-02-21 23:33:49 +01:00
Florent Kermarrec acdf511bd1 doc: remove IP 2015-02-21 23:33:21 +01:00
Florent Kermarrec 7837580020 add ft2232h software code (will need rework) 2015-02-21 23:19:10 +01:00
Florent Kermarrec b59c777cab add ft2232h hdl code (will need rework) 2015-02-21 23:13:43 +01:00
Florent Kermarrec 1b0bc5ca44 init repo structure 2015-02-21 23:06:36 +01:00
Florent Kermarrec 4bdb1ffda2 add README skeleton 2015-02-21 22:58:42 +01:00
Florent Kermarrec 65294a5577 add tty over udp (will need mac to insert padding) 2015-02-21 21:26:52 +01:00
Florent Kermarrec 0a9043b6c1 remove MiSoC dependency 2015-02-21 19:34:14 +01:00
Florent Kermarrec 52f5955dca remove MiSoC dependency 2015-02-21 19:29:26 +01:00
Florent Kermarrec 741ecca5b4 la: fix intput_buffer clocking when clk_domain is not "sys" 2015-02-19 11:41:54 +01:00
Florent Kermarrec 37e463da9a fix rle when used with subsampler 2015-02-19 11:34:20 +01:00
Florent Kermarrec e495e2f537 driver/la: add samplerate computation (required by sigrok export) 2015-02-19 11:16:32 +01:00
Florent Kermarrec 8e0553670a remove limitation on debug tuple definition 2015-02-19 10:52:57 +01:00
Florent Kermarrec 5f19955825 rle: expose length parameter to user, add assertion on dw to encode counter and automatically increase dw in rle mode 2015-02-19 10:42:13 +01:00
Florent Kermarrec 5fb6beb473 enable RLE only in POST_HIT_RECORDING state (to ensure programmed offset is respected) 2015-02-19 10:26:34 +01:00
Florent Kermarrec 788652c6f8 simplify RLE 2015-02-19 01:43:04 +01:00
Florent Kermarrec 87f29a307a fix typo 2015-02-18 23:35:50 +01:00
Florent Kermarrec 3680b48216 dump/sigrok: fix against real dumps, now able to import and export 2015-02-18 21:45:36 +01:00
Florent Kermarrec 6db831e5a8 update LiteX 2015-02-18 11:39:22 -07:00
Florent Kermarrec 73ab271f9a targets/kc705: fix csr address conflict on eth 2015-02-18 10:45:18 -07:00
Florent Kermarrec 0a38b8c74a add LiteX external core and remove ethmac 2015-02-18 10:43:44 -07:00
Florent Kermarrec 9ebb8f8022 remove verilog and move mxcrg.v to misoclib/mxcrg 2015-02-18 10:40:30 -07:00
Florent Kermarrec 5500c41915 move lm32/mor1kx submodules to extcores 2015-02-18 10:39:18 -07:00
Florent Kermarrec 4c9554b65c gensoc: call do_exit after SoC is built 2015-02-18 10:38:14 -07:00
Florent Kermarrec 9326985e05 update LiteScope 2015-02-18 16:53:02 +01:00
Florent Kermarrec e6f1bdb152 update LiteScope 2015-02-18 16:51:35 +01:00
Florent Kermarrec 6bfd5ce1d8 split host files since we now have more drivers/dumps supported 2015-02-18 16:49:38 +01:00
Florent Kermarrec 08935dce9a make.py: add powered by Migen 2015-02-18 16:39:18 +01:00
Florent Kermarrec e17791a85b readme/make.py: add powered by Migen 2015-02-18 16:38:48 +01:00
Florent Kermarrec 2f6465d439 add sigrok import (to check export against it) 2015-02-18 15:23:04 +01:00
Florent Kermarrec 130212039e continue sigrok export (should almost work) 2015-02-18 11:59:35 +01:00
Florent Kermarrec cd43163d9d add sigrok export skeleton (wip) 2015-02-18 00:44:33 +01:00
Florent Kermarrec 70f94ea0eb logo : add powered by Migen 2015-02-17 23:17:46 +01:00
Florent Kermarrec 89eaef0e43 logo : add powered by Migen 2015-02-17 23:16:06 +01:00
Florent Kermarrec 5830575797 logo : add powered by Migen 2015-02-17 23:14:21 +01:00
Florent Kermarrec 79a7f9ecb8 create BaseSoC as a basic example design and build UDPSoC/EtherboneSoC on top of it 2015-02-17 12:37:17 +01:00
Florent Kermarrec eeaf03669a test: we can now test regs with Etherbone 2015-02-17 01:15:06 +01:00
Florent Kermarrec a5416fa864 host: add Etherbone driver 2015-02-17 01:09:53 +01:00
Florent Kermarrec 1a3183c15d etherbone: fix addressing 2015-02-17 00:02:49 +01:00
Florent Kermarrec 67958f7448 mac: fix missing core csr generation 2015-02-16 14:44:36 +01:00
Florent Kermarrec da13bd536e gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8 2015-02-14 03:24:23 -08:00
Florent Kermarrec 3559de9b4c add setup.py 2015-02-14 02:44:39 -08:00
Florent Kermarrec d3cf2594f2 update download instructions 2015-02-12 22:03:24 +01:00
Florent Kermarrec b64dba7a81 update download instructions 2015-02-12 22:03:04 +01:00
Florent Kermarrec aedc964908 update download instructions 2015-02-12 22:02:50 +01:00
Florent Kermarrec 04f7fbd7e2 simplify litescope export with do_exit call and remove automatic clean 2015-02-12 21:15:51 +01:00