07cfda119d
interconnect/wishbone: check err in simulation
2024-04-05 12:35:47 +11:00
416f1b4281
cores/spi_mmap: add slot post transfer cs_wait
...
Also remove unused slot_status - maintains CSR alignment now that
slot_control is 64 bit (two 32bit registers).
2024-04-05 12:35:47 +11:00
f3b287addd
cores/spi_mmap: add 24-bit slot length
2024-04-05 12:31:39 +11:00
5d1fa7b6ca
cores/spi_mmap: fix data if bus width > length
...
Details:
* 32bit bus write to 8 and 16bit MSB first slot resulted
in shifted data on mosi.
* 32bit read from 8 and 16bit LSB first slot resulted
with shifted data in fifo.
Fixes 2 tests - all current tests now pass.
2024-04-05 12:31:39 +11:00
422b02cc16
cores/spi_mmap: fix data in unused rx_fifo bits
...
clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.
2024-04-05 12:31:39 +11:00
a9c007d8d7
test/spi_mmap: add some SPIMMAP tests
...
Some pass and some fail demonstrating issues observed in driver
development.
run unittest with -v to see more test details.
Ran 9 tests in 4.161s
FAILED (failures=4)
2024-04-05 12:31:39 +11:00
4bc47c959f
test/spi_mmap: lint and autoformat with Ruff
2024-04-05 12:31:39 +11:00
2e67f6a1a3
soc/cores/spi_mmap: add read only slot count register
2024-04-05 12:31:39 +11:00
3477aeaca1
soc/cores/spi_mmap: add read only version register
2024-04-05 12:31:39 +11:00
6170c90459
soc/cores/spi_mmap: adjust CSR mapping to better suit drivers
...
Currently the TX_RX_ENGINE CSR register lives below the
slot registers which are dynamic in length (based on how
many slots (chip selects) are configured in the gateware).
Move the TX_RX_ENGINE CSR to above the SLOT configuration
registers so TX_RX_ENGINE never moves.
This makes for an easier and cleaner driver.
2024-04-05 12:31:39 +11:00
dc78c3f47b
soc/interconnect/stream/ClockDomainCrossing: Add a Buffer when same Clk Domains when buffered=True.
2024-04-04 13:02:17 +02:00
a36fbc86ea
Merge pull request #1911 from davidar/sim-vsync
...
sim/video: Add option to render only on frame vsync
2024-04-02 10:54:05 +02:00
7ad444b2a9
Merge pull request #1912 from motec-research/efinity_fix_pin_name
...
build/efinix/platform: fix get_pin_name()
2024-04-02 10:48:19 +02:00
38a8a171dd
integration/builder: Replace soc_core's initialize_memory with optional "init_mems" method.
...
Make sure to also attach Builder to SoC to allow easily get/use builder properties in init_mems method.
2024-04-02 10:43:01 +02:00
31508ddfa4
soc: Add separators for SoC Main Components.
2024-04-02 10:25:59 +02:00
06083c7863
soc/init_ram: Define and use contents_size.
2024-04-02 10:21:35 +02:00
ca04858b39
integration/builder: Switch to SoC.init_rom directly and remove initialize_rom that is no longer used.
2024-04-02 10:16:43 +02:00
175aab73a8
soc/SoC: Add init_ram method from init_rom, allowing initilization of any RAM of the SoC and switch init_rom to it.
2024-04-02 10:09:38 +02:00
9f49b13f8c
soc_core: Minor cosmetic changes.
2024-04-02 09:15:33 +02:00
f181eabebb
soc/init_rom: Add SoCError when ROM Size < Contents Size and cosmetic cleanups.
2024-04-02 09:12:03 +02:00
0601bf51c4
Merge pull request #1856 from motec-research/soc_initialize_memory
...
soc/builder: add initialize_memory()
2024-04-02 17:30:12 +11:00
0cb101da25
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-04-02 11:52:31 +11:00
a763e82d86
soc/builder: add initialize_memory()
...
Allows the target soc to override memory initialization:
rom and/or ram.
2024-04-02 11:37:31 +11:00
5d2676482f
sim/video: Add option to render only on frame vsync
2024-03-29 11:24:16 +10:00
87137c3027
CHANGES.md: Update.
2024-03-28 14:24:12 +01:00
7b0985a6bc
Merge pull request #1909 from davidar/sim-rgba
...
sim/video: Change pixel format to RGBA
2024-03-28 14:21:24 +01:00
c73f310179
Merge pull request #1908 from Irvise/neorv32_update
...
Update NeoRV32 CPU to v1.9.7
2024-03-28 14:20:59 +01:00
206118c427
Add missing file
2024-03-28 09:16:25 +01:00
c7b2393e34
nax jtag renaming
2024-03-28 09:16:19 +01:00
60920f3c7d
integration/export: Also fix MockCSRRegion base definition.
2024-03-27 17:09:33 +01:00
e74b7f7ebe
integration/export: Fix MockCSRRegion C header export.
...
Use full address for export since when used, CSR_BASE is related to the top level SoC and not to the imported external mapping.
2024-03-27 16:49:09 +01:00
1895dd36e2
tools/litex_sim: Add --with-video-colorbars option
2024-03-26 20:23:51 +10:00
6735728340
sim/video: Change pixel format to RGBA
2024-03-26 20:22:58 +10:00
4389742a4f
CHANGES.md: Update.
2024-03-25 19:10:40 +01:00
40ff2da45c
Update NeoRV32 CPU to v1.9.7
2024-03-23 10:18:07 +01:00
9156d7902e
tools/litex_json2dts_linux: increment interrupts value by one for rocket
2024-03-21 20:54:08 +01:00
68108e396d
tools/litex_json2dts_linux: added isa-base,isa-extensions required by kernel > 6.6.0 in replacement to isa
2024-03-21 20:53:19 +01:00
473c52c9d8
Got jtag instruction interface to work
2024-03-21 13:29:40 +01:00
72cb7d3fb7
Fix jtag reset
2024-03-21 13:05:18 +01:00
29aa8f0771
Merge pull request #1906 from jdavidberger/master
...
Avoid extra timing delays for NXLRAM path
2024-03-21 09:14:39 +01:00
c640efcec3
Avoid extra timing delays for NXLRAM path
2024-03-20 14:58:08 -06:00
90c1d7b62d
Update the reset topology
2024-03-20 17:56:53 +01:00
edc24b39a4
Got linux + jtag to run in sim
2024-03-20 17:37:51 +01:00
8f04542c15
Revert "build/openocd: Allow config file to be searched from local dirs"
...
This reverts commit a7d441488c
2024-03-20 16:44:58 +01:00
46ff7cdee5
Merge pull request #1901 from FlyGoat/zynq7000_openocd
...
Zynq7000 litex_server OpenOCD JTAG fixes
2024-03-20 16:41:22 +01:00
d7a862fdd0
wip
2024-03-20 08:09:30 +01:00
9d0fc2c7c2
litex_json2dts_linux: Add support for multiple Ethernet interfaces
2024-03-12 14:42:48 +01:00
c2fd1e9a49
litex_json2dts_linux: Switch to cpu_name instead of cpu_human_name.
2024-03-08 18:53:44 +01:00
49f12ea297
soc/add_cpu: Add CPU_NAME constant.
2024-03-08 18:51:26 +01:00
a7d441488c
build/openocd: Allow config file to be searched from local dirs
...
To sort out path for boards using OpenOCD config file shipped with
OpenOCD itself.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-07 19:54:04 +00:00
Andrew Dennison
Richard Tucker
Florent Kermarrec
AndrewD
David A Roberts
Dolu1990
Fernando Oleo Blanco
Gwenhael Goavec-Merou
jdavidberger
Gwenhael Goavec-Merou
inc
Jiaxun Yang