Commit Graph

3364 Commits

Author SHA1 Message Date
Tim 'mithro' Ansell 514496d744 libcompiler_rt: Fixing Makefile for CPU endianness. 2016-04-19 14:55:01 +10:00
Tim 'mithro' Ansell e7f3c585b7 Allow using gcc for or1k.
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
2016-04-19 14:03:24 +10:00
Tim 'mithro' Ansell 2f834d0aa2 bios: Use single characters for boot modes.
* The function keys never really worked properly.
 * Also add commands for the ROM/Flash/etc.
2016-04-19 13:42:56 +10:00
Florent Kermarrec 429f533bd0 soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
Florent Kermarrec 7b3699839e build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint 2016-04-14 21:48:52 +02:00
Florent Kermarrec 3d222d9e63 soc/interconnect/dma_lasmi: change endpoint names 2016-04-13 18:28:52 +02:00
Florent Kermarrec 6e0045e6be soc/integration/soc_sdram: allow passing controller settings in register_sdram 2016-04-12 20:16:47 +02:00
Florent Kermarrec 40eb779e67 software/include/base: fix system.h for or1k 2016-04-10 17:21:54 +02:00
Florent Kermarrec 238d69f186 software/common: use -std=gnu99 for GCC 2016-04-10 17:21:17 +02:00
Florent Kermarrec b2eaf412c1 soc/interconnect/stream/PipelinedActor: add latency attribute 2016-04-07 12:10:32 +02:00
Florent Kermarrec 9fa9bdcf68 build/sim: adapt verilator simulation to new stream signals 2016-04-07 08:56:53 +02:00
Florent Kermarrec 8ced064160 soc/software/libcompiler_rt: fix mulsi3 compilation 2016-04-07 08:28:38 +02:00
Florent Kermarrec 80d78698e3 soc/software/libnet/microudp: fix debug flag 2016-04-07 08:28:38 +02:00
Florent Kermarrec 17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec 7e62cdf601 soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100) 2016-03-31 10:55:11 +02:00
Florent Kermarrec 1d4f44e7db soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores 2016-03-31 00:02:22 +02:00
Florent Kermarrec b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
Florent Kermarrec 7cd83c420f README: update 2016-03-28 23:05:16 +02:00
Florent Kermarrec f512971d9e gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop) 2016-03-25 13:22:26 +01:00
Florent Kermarrec 0ef1d44c44 gen/sim, fhdl: remove port.we_granularity limitation on simulations
We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.

If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.
2016-03-23 09:46:54 +01:00
Florent Kermarrec 9517b9b870 soc/interconnect/stream_sim: use passive generators and some cleanup 2016-03-23 01:04:33 +01:00
Florent Kermarrec 5e16516706 gen: add missing sim files 2016-03-21 23:52:52 +01:00
Florent Kermarrec dd2397b57c gen: remove vpi (no longer used) 2016-03-21 20:07:03 +01:00
Florent Kermarrec cf29ee0b91 soc/interconnect/stream_sim: adapt to new simulator 2016-03-21 19:56:43 +01:00
Florent Kermarrec 703b30e078 gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator
* fhdl/visit: determinism
* structure/Case/makedefault: fix corner cases
* fhdl/tools: apply lowerer to specials in deterministic order
* fhdl/verilog: fix variable name conflict
* fhdl/verilog: simpler names for IOs. Closes #40
* fhdl/namer: deterministic naming of signals with name_override
* use https url for m-labs.hk
* pipistrello: make PMOD an extension header
* vivado: find clock nets by get_nets, not get_ports
* build: support platform-independent false path designation
* sim: add more signals to VCD (#36)
* build/xilinx: fix error message when Xilinx toolchain directory exists but does not contain a ISE version directory. Closes #39
* kc705: make xadc an extension header
* kc705: add xadc/ams gpios
* Merge branch 'master' of github.com:m-labs/migen
* conda: fix for conda-build > 1.19
* platforms/kc705: enable on-die termination for user_sma_clock
* README: update
* Revert "conda: use BUILDNUMBER from environment."
This reverts commit b2eedfd2e24f0b83c2fb118a3f98cf349b256e91.
* conda: use BUILDNUMBER from environment.
* typo
* Exception now has helpful string.
* README: remove outdated build badge
* sim: run MemoryToArray before lowering specials
* fhdl/simplify/MemoryToArray: remove spurious memory ports from specials
* sim: make unlowered specials an error
* sim: lower specials, closes #34
* sim: support evaluating Replicate()
* Revert "README.md->rst"
* Prevent backslashes in (Windows) paths from being escaped by OpenOCD's TCL implementation.
* Revert "conda: run tests as a part of package build."
* Revert "setuptools: include examples as migen.examples."
* Revert "test: also look for examples in [.../dist-packages]/migen/examples/."
* conda: use source from the current checkout.
* travis: disable (superseded by our buildbot).
* test: also look for examples in [.../dist-packages]/migen/examples/.
* setuptools: include examples as migen.examples.
* conda: run tests as a part of package build.
* build: return to current working directory after building
* sim/vcd: support signals not appearing in FHDL
* sim: deterministic clock iteration
* sim: add support for passive generators
* fhdl/structure: fix last test in _Value.__bool__ (a instead of b)
2016-03-21 19:15:40 +01:00
Florent Kermarrec 71a719be44 soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
Florent Kermarrec 9032665750 soc/interconnect/wishbonebridge: fix import 2016-03-16 19:34:50 +01:00
Florent Kermarrec d7112efdba soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now) 2016-03-16 19:33:29 +01:00
Florent Kermarrec 39aacf2df4 soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring 2016-03-16 19:33:00 +01:00
Florent Kermarrec e0e2427795 soc: replace all Sink/Source with stream.Endpoint 2016-03-16 18:05:57 +01:00
Florent Kermarrec c860581b86 soc/interconnect/stream: use new Converter/StrideConverter 2016-03-16 17:00:58 +01:00
Florent Kermarrec 8c272c1f6f soc/interconnect/stream: fix missing param 2016-03-16 16:21:32 +01:00
Florent Kermarrec cb47373383 soc/interconnect/stream: remove packetized parameter and use of sop 2016-03-16 11:54:28 +01:00
Florent Kermarrec 44a5b95281 soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter) 2016-03-15 15:52:57 +01:00
Florent Kermarrec a016ededa0 soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert) 2016-03-04 20:56:05 +01:00
Florent Kermarrec 042c36ee1b soc/tools/litex_term: continue cleanup 2016-02-19 17:44:25 +01:00
Florent Kermarrec 2fa848c15f soc/tools/litex_term: continue cleanup 2016-02-19 14:35:18 +01:00
Florent Kermarrec 247ecc5d8a soc/tools/litex_term: continue cleanup 2016-02-19 13:38:34 +01:00
Florent Kermarrec ed2e623994 soc/tools/litex_term: remove write_exact, use more bytes 2016-02-19 00:20:10 +01:00
Florent Kermarrec 4bdefbdfba soc/tools/litex_term: remove character function 2016-02-19 00:02:38 +01:00
Florent Kermarrec 5b8566d20f soc/tools/litex_term: replace get_file_data with f.read() 2016-02-18 23:55:41 +01:00
Florent Kermarrec 68c2d3b7a0 soc/tools/remove: fix import 2016-02-18 12:55:18 +01:00
Florent Kermarrec fd2997bf4a build/xilinx: cleanup Vivado/ISE special_overrides 2016-02-18 00:36:53 +01:00
Florent Kermarrec 8ee3874088 soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master 2016-02-18 00:11:25 +01:00
Florent Kermarrec 34b45e3618 gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework) 2016-02-11 22:54:26 +01:00
Florent Kermarrec 2218ece98a soc/interconnect/stream: fix merge issue (missing params connect) 2016-02-01 00:08:27 +01:00
Florent Kermarrec 6c71811138 soc/tools/litex_term: also rename inside file 2016-01-16 21:26:33 +01:00
Florent Kermarrec 601c91a3e2 soc/tools: rename to litex_term, litex_server, litex_client 2016-01-16 21:22:21 +01:00
Florent Kermarrec 162900144a soc/tools/remove_server: cleanup 2016-01-16 21:12:19 +01:00
Florent Kermarrec b856b54720 soc/tools/flterm: get rid of serial.tools.miniterm import and fix echo on linux 2016-01-16 21:05:03 +01:00