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7895 Commits

Author SHA1 Message Date
Navaneeth 0fbaa51c71 Change to common isr handler 2021-10-19 07:14:36 +05:30
Andrew Dennison 053e540b8a soc/csr: ValueError if write would be truncated in simulation 2021-10-19 10:42:52 +11:00
Andrew Dennison 04e9ffa2b2 soc/csr: Document simulation side effects of read/write 2021-10-19 10:42:52 +11:00
Florent Kermarrec 467c1b9b88 builder: Move Meson check to _check_meson and only do it when using BIOS. 2021-10-18 18:48:47 +02:00
Navaneeth ef8bab4c11 Add support for Ibex interrupt 
Initial support for a working Ibex interrupt. Tested in Verilator.
 2021-10-18 20:02:05 +05:30
Florent Kermarrec 2a109c3a3e integration/builder: Add Meson install/version check. 2021-10-18 08:41:51 +02:00
Florent Kermarrec f92a185109 litex_setup: Fix git checkout to specific version (we are using short sha1 hashes). 2021-10-18 08:19:11 +02:00
navaneeth c8a83461b4 Add initial changes to add IRQ support 
In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.
 2021-10-17 12:32:31 +05:30
navaneeth b2b0ba66e5 Fix the support for Ibex. 
Take care of the module change in instantiation of Ibex core.
 2021-10-16 16:29:00 +05:30
enjoy-digital 57002cf3fc
Merge pull request #1069 from trabucayre/efinix_timing_model 
efinix: don't hardcode timing model
 2021-10-16 08:48:19 +02:00
Gwenhael Goavec-Merou 627363906c efinix: don't hardcode timing model 2021-10-16 07:20:17 +02:00
Florent Kermarrec 306bdcaed8 fhdl/verilog: Fix regression introduced in to_signed function. 2021-10-15 21:46:42 +02:00
enjoy-digital 942d3165bd
Merge pull request #1068 from mmicko/efinix_pgm_fix 
efinix: set defaults for efx_pgm pass
 2021-10-15 17:42:12 +02:00
Miodrag Milanovic 8692ddfbff Set defaults for efx_pgm pass 2021-10-15 16:40:01 +02:00
Florent Kermarrec 37dd6c1edb fhdl/verilog: Update header. 2021-10-15 15:25:23 +02:00
Florent Kermarrec 3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX). 2021-10-15 15:20:01 +02:00
Florent Kermarrec fe2998a19c fhdl/verilog: Remove create_clock_domains (not used in LiteX). 2021-10-15 15:12:30 +02:00
Florent Kermarrec 8c3508e7f5 fhdl/verilog: Remove dummy_signal (no longer used). 2021-10-15 15:09:41 +02:00
Florent Kermarrec f692f50d06 fhdl/verilog: Remove reg_initialization (always enabled in LiteX). 2021-10-15 15:01:41 +02:00
Florent Kermarrec 84e8fd0f9e fhdl/verilog: Add larger separators. 2021-10-15 14:55:46 +02:00
Florent Kermarrec 5a2399b037 fhdl/verilog: Remove display_run (not used in LiteX). 2021-10-15 14:43:42 +02:00
Florent Kermarrec 8aad25ae2b fhdl/verilog: Create _print_cat/_print_replicate, start cleaning up convert. 2021-10-15 14:25:33 +02:00
Florent Kermarrec 2c98ad94b5 fhdl/verilog: Create _print_operator/_print_slice, move code outside _print_expression and cleanup/simplify. 2021-10-15 13:54:06 +02:00
Florent Kermarrec cdfb8d141a fhdl/verilog: Simplify _print_signal/_print_constant, add comments to _print_expression. 2021-10-15 11:51:39 +02:00
Florent Kermarrec a18107f795 fhdl/verilog: Give more explict names to print functions. 2021-10-15 11:27:34 +02:00
Florent Kermarrec 86178ed2d9 fhdl/verilog: Update Reserved Keywords (from IEEE 1800-2017) and minor cleanup. 2021-10-15 11:06:31 +02:00
Michal Sieron 5b166b3aa4 Fix microwatt synthesis 
Microwatt uses now 29 bit wishbone addresses, so 3 additional bits for
compatibility are no longer needed.

Rest is minimal set of changes that was needed to make it build.
 2021-10-14 19:57:11 +02:00
Florent Kermarrec adf30928d4 build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog. 2021-10-14 19:12:00 +02:00
Florent Kermarrec 2628140e8a soc_core: Also add "no_we" support to integrated_main_ram (and improve add_ram/add_rom calls). 2021-10-14 10:18:17 +02:00
Florent Kermarrec 8316fbf14b build/efinix/common: Fix EfinixAsyncResetSynchronizerImpl. 
SR_VALUE is set to 0 by default and needs to be set to 1.
 2021-10-13 16:31:47 +02:00
Florent Kermarrec f0a3fcfefa build/efinix: Improve error message when Efinity toolchain is not found. 2021-10-13 14:41:44 +02:00
Florent Kermarrec fd354c5759 gen/fhdl/memory: Fix dual clock memory pattern (previous pattern is no longer supported by Yosys), thanks @gregdavill. 
See https://github.com/enjoy-digital/litex/issues/1003.
 2021-10-13 11:33:43 +02:00
Florent Kermarrec 8fbd1b84a4 gen/fhdl: Use a local emit_verilog function for Memory. 
With the various FPGA now supported, being able to generate valid verilog patterns
that will be infered correctly is now complicated.

Use our local version of emit_verilog to be able to specialize more easily the generated
code.

This will also allow use to progressively remplace Migen's Memory.
 2021-10-13 10:58:49 +02:00
Florent Kermarrec 269b84eca4 build/efinix: Move tweaked Memory to build/efinix for now. 2021-10-13 09:51:47 +02:00
Florent Kermarrec a99b4cac48 build/efinix: Minor initial cleanups. 2021-10-13 09:42:39 +02:00
enjoy-digital eafa0fe83e
Merge pull request #1066 from fjullien/efinix 
Initial Efinix support.
 2021-10-13 09:17:32 +02:00
Florent Kermarrec 5e3e78f760 soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness. 2021-10-12 15:46:35 +02:00
enjoy-digital f93b6b9f27
Merge pull request #1065 from shenki/microwatt-picolibc-family 
microwatt: Fix family property
 2021-10-12 09:08:57 +02:00
Florent Kermarrec a489dadfbc cpu/CPUNone: Add ethmac to mem_map as temporary build workaround for --cpu-type=None --with-ethernet. 2021-10-12 09:02:48 +02:00
Joel Stanley 79ae6a99ab microwatt: Fix family property 
In commit 061b89beff ("cpu/picolibc: Add family property to CPUs and
directly use it for picolibc.") a family was added for meson cross
compilation, but this doesn't exist, leading to the following warning:

 WARNING: Unknown CPU family powerpc, please report this at https://github.com/mesonbuild/meson/issues/new

Instead use ppc64. While this seems wrong for a ppc64le machine, it
appears to be what meson expects.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-10-12 17:21:09 +10:30
Florent Kermarrec 96cfb44851 soc: Raise custom SoCError Exception and disable traceback/exception since already described. 2021-10-12 08:35:14 +02:00
enjoy-digital 975ec20d1e
Merge pull request #1061 from osterwood/patch-1 
Update icestorm.py with u4k device, since Yosys can target it
 2021-10-11 10:21:23 +02:00
Chris Osterwood 665665e1cc
Update icestorm.py with u4k device, since Yosys can target it 2021-10-08 15:20:39 -04:00
Florent Kermarrec db20cb172d cores/video/VideoFrameBuffer: Add missing ClockDomainsRenamer on Converter (thanks @rdolbeau). 
Converter was not running in the right clock domain in ((dram_port.data_width > depth) and clock_faster_than_sys) case.
 2021-10-08 14:33:04 +02:00
Florent Kermarrec f508b131ea cores/video: Change depth parameter to format (more explicit and we'll maybe want to support other video formats). 2021-10-08 14:28:04 +02:00
enjoy-digital 6d317d0882
Merge pull request #1053 from rdolbeau/fb_rgb565 
Add 16-bits, RGB565 FB support in simple-framebuffer
 2021-10-08 14:15:10 +02:00
Florent Kermarrec 9f0a03100d litex_setup: Add more comment, fix checkout when sha1 starting with 0. 2021-10-07 19:03:29 +02:00
gsomlo 1629bcbf30
Merge pull request #1058 from gsomlo/gls-rocket-smp-ecp5 
cpu/rocket: add dual-core (smp) variants
 2021-10-07 09:04:08 -04:00
Gabriel Somlo 18bd8f3770 cpu/rocket: add dual-core (smp) variants 
- 2-core "linux" (fpu-less) variants with double, quad mem. bus width
 2021-10-06 08:48:27 -04:00
Florent Kermarrec f03a15820b tools/litex_sim: Remove useless pre_run_callback toolchain attribute. 2021-10-06 09:16:08 +02:00