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9017 Commits

Author SHA1 Message Date
Dolu1990 8e7fd9bc1f Merge branch 'master' into naxriscv-merge 2022-09-12 19:18:12 +02:00
Florent Kermarrec 23f529a313 soc/builder: Propagate data_width to get_mem_data. 2022-09-12 16:46:20 +02:00
Florent Kermarrec 481234de91 integration/common/get_mem_data: Add data_width support. 2022-09-12 16:45:55 +02:00
Florent Kermarrec a7cc1af416 soc: Propagate main bus address_width to the different interfaces dynamically created. 2022-09-12 16:13:45 +02:00
Florent Kermarrec 95bed6de5c interconnect/wishbone: Allow passing address_width (In byte addressing). 
This is useful to abstract interfaces and propagate address_width.

Idealy, Wishbone should be fully switch to byte addressing since word addressing
has been a source of common issues/errors in the past but compatibility issues
would need to be evaluated first.
 2022-09-12 16:12:52 +02:00
Florent Kermarrec 91c521a22a Changes: Prepare for next release changes. 2022-09-12 11:08:50 +02:00
Florent Kermarrec ded3bad178 cpu/naxriscv: Minor cleanups on recent changes. 2022-09-12 11:01:42 +02:00
Dolu1990 f2a088bfcc
Merge pull request #1355 from cklarhorst/master 
integration/soc Add accessible_region to add_memory_buses
 2022-09-12 10:18:22 +02:00
Florent Kermarrec fa0c2df687 CHANGES: Update and release. 2022-09-12 09:00:36 +02:00
Vegard Storheil Eriksen 3c4c12a72f cores/dma: End transfer when the last flag is set. 2022-09-10 10:15:37 +02:00
Vegard Storheil Eriksen 6ad6d1e414 cores/dma: Don’t drop data while idle. 2022-09-10 10:15:37 +02:00
Christian Klarhorst 6367fc6cab update naxriscv comments 2022-09-09 13:19:36 +02:00
Florent Kermarrec 15f72174ce interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels. 2022-09-09 12:46:31 +02:00
Dolu1990 14160ce7e3 cpu/NaxRiscv update nax with peripheral memory region 2022-09-09 11:23:24 +02:00
Florent Kermarrec b7e2d24f37 interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle. 2022-09-08 17:41:24 +02:00
Christian Klarhorst a04f20880f Change naxriscv memory-region format 
It now has a mode and a bus field.
modes: rwxc (read, write, execute, cachable)
bus: pm (peripheral, memory)
 2022-09-08 17:33:20 +02:00
Florent Kermarrec e5de4b356a interconnect/axi/axi_lite: Add prot signal. 
Not directly used by LiteX but useful for wrapping AXI-Lite RTL code.
 2022-09-08 12:06:35 +02:00
Florent Kermarrec 3b714c8145 test: Add minimal test_axi_stream test (Just syntax check for now). 2022-09-08 11:53:05 +02:00
Florent Kermarrec afc89c9350 interconnect/axi/axi_stream: Add ID/Dest support and minor cleanup. 2022-09-08 11:51:55 +02:00
Florent Kermarrec 5b8d3651a9 software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar). 2022-09-07 16:27:54 +02:00
Florent Kermarrec ee536f9cd5 CONTRIBUTORS: Update. 2022-09-07 10:13:17 +02:00
Florent Kermarrec 85e8aab5ae tools/litex_contributors: Sort contributors by names. 
The git .csv generation is already sorted but this needs to be sorted again due
to the companies renaming.
 2022-09-07 10:07:12 +02:00
Florent Kermarrec 0bd19fd026 tools/litex_contributors: Rename authors to contributors. 2022-09-07 09:49:26 +02:00
Florent Kermarrec 0144612751 tools/litex_contributors: Add RapidSilicon to companies. 
RapidSilicon is helping funding the improvement/development of LiteX features
and the team also contribute directly to the project.
 2022-09-07 09:48:27 +02:00
Florent Kermarrec 4d6813ae64 tools/litex_contributors: Sort years. 2022-09-07 09:42:20 +02:00
Florent Kermarrec a6acfb9a37 stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests. 
Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
 2022-09-07 08:59:37 +02:00
Dolu1990 ce90181046 cpu/VexRiscv_SMP add --wishbone-force-32b option 2022-09-06 13:13:45 +02:00
Dolu1990 af43e98e78 Merge branch 'naxriscv-merge' 2022-09-06 13:07:54 +02:00
Dolu1990 5fad94f9d6 cpu/VexRiscv_SMP add --wishbone-force-32b option 2022-09-06 11:23:36 +02:00
Florent Kermarrec 36297c7a1e cores/video: Avoid serializer_attrs. 2022-09-05 09:49:15 +02:00
enjoy-digital 398811b910
Merge pull request #1413 from trabucayre/gowin_HDMI 
soc/cores/video: adding Gowin HDMI Phy
 2022-09-05 09:32:29 +02:00
enjoy-digital 8159b5caad
Merge pull request #1412 from umarcor/umarcor/f4pga 
litex/build/xilinx/f4pga: update imports
 2022-09-02 19:03:02 +02:00
Gwenhael Goavec-Merou a9c7e868e7 soc/cores/video: adding Gowin HDMI Phy 2022-09-02 19:00:33 +02:00
umarcor 7f17866386 litex/build/xilinx/f4pga: update imports 
Signed-off-by: umarcor <umartinezcorral@antmicro.com>
 2022-09-02 15:48:22 +02:00
Florent Kermarrec 153182a014 cores/dna: Fix typo. 2022-09-02 13:09:40 +02:00
Christian Klarhorst c8bd747e0f Remove linker regions from naxriscv mem list 
Assume linker=True SoCRegions are virtual only.
 2022-09-02 12:13:21 +02:00
Florent Kermarrec 4426e61899 soc/add_pcie: Expose with_synchronizer parameter. 2022-09-01 17:47:27 +02:00
Florent Kermarrec b24d744f8e cores/dna: Rewrite/simplify core and use a slower clock (sys_clk/16). 2022-09-01 14:24:01 +02:00
Florent Kermarrec 1c4d64f46b CHANGES: Update. 2022-09-01 11:22:25 +02:00
Christian Klarhorst b63e445ade cpu/NaxRiscv: Update to new version 2022-08-31 15:31:37 +02:00
Christian Klarhorst 6cbeed6f73
Merge branch 'enjoy-digital:master' into master 2022-08-31 13:27:32 +02:00
Christian Klarhorst fb2a52a6c7 Generate naxriscv mem region parameters in new format 2022-08-31 13:25:27 +02:00
Florent Kermarrec c0d3775dcd integration/builder: Simplify bios_console. 2022-08-31 12:10:15 +02:00
Florent Kermarrec aec02b395d integration/builder: Add default bios_console value. 2022-08-31 10:33:26 +02:00
Florent Kermarrec 35afd59956 tools/litex_server/litex_client: Add initial information exchange and improve PCIe case. 
Due to the address translation done with the LitePCIe bridge (remapping CSR to 0), RemoteClient
needs to know which bridge is used to also translate CSRs.

This commit adds an initial information exchange between server and client and avoid the PCIe workarounds.
 2022-08-30 18:54:03 +02:00
Christian Klarhorst 027306972a Naxriscv now scans for executable mem regions and forwards that info to the scala build process 
Format:
--scala-args=executable-region=(origin, length), --scala-args=exe...
 2022-08-30 16:41:39 +02:00
Christian Klarhorst 3e42133abd Change SDRAM region to RWX 2022-08-30 16:22:29 +02:00
Christian Klarhorst 76c0754d1e Add new SocRegion mode "x" (executable) 
Defaults:
SoCRegion/SoCIORegion/SoCCSRRegion: RW
ROMs: RX
RAMs: RWX
 2022-08-30 15:57:25 +02:00
Christian Klarhorst 37360587e3 Change SocRegion readonly definition 
From (mode == "r") to ("w" not in mode).
This allows to have more possible modes than r & w.
 2022-08-30 15:47:59 +02:00
enjoy-digital ea8ba57eab
Merge pull request #1410 from trabucayre/improve_connectors 
Improve connectors
 2022-08-30 15:34:55 +02:00